DATA SHEET
256M bits SDRAM Bare Chip
ECS2532CACN-A (8M words × 32 bits)
Features
• Density: 256M bits
• Organization
⎯ 2M words × 32 bits × 4 banks
• Package: Bare chip
• Power supply: VDD, VDDQ = 2.5V ± 0.2V
• Clock frequency: 133MHz (max.)
• 2KB page size
⎯ Row address: A0 to A11
⎯ Column address: A0 to A8
• Four internal banks for concurrent operation
• Interface: LVTTL
• Burst lengths (BL): 1, 2, 4, 8, full page
• Burst type (BT):
⎯ Sequential (1, 2, 4, 8, full page)
⎯ Interleave (1, 2, 4, 8)
• /CAS Latency (CL): 2, 3
• Precharge: auto precharge operation for each burst
access
• Refresh: auto-refresh, self-refresh
• Refresh cycles: 4096 cycles/64ms
⎯ Average refresh period: 15.6μs
• Operating ambient temperature range
⎯ TA = 0°C to +70°C
• ×32 organization
• Single pulsed /RAS
• Burst read/write operation and burst read/single write
operation capability
• Byte control by DQM
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Specifications
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Document No. E0551E30 (Ver. 3.0)
Date Published December 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
This product became EOL in March, 2007.
©Elpida Memory, Inc. 2004-2005
