FDS6900S
Dual N-Ch PowerTrench SyncFet™
General Description
Features
The FDS6900S is designed to replace two single SO-8
MOSFETs and Schottky diode in synchronous DC:DC
power supplies that provide various peripheral voltages
for notebook computers and other battery powered
electronic devices. FDS6900S contains two unique
30V, N-channel, logic level, PowerTrench MOSFETs
designed to maximize power conversion efficiency.
•
Q2:
Optimized to minimize conduction losses
Includes SyncFET Schottky body diode
RDS(on) = 22mΩ @ VGS = 10V
8.2A, 30V
RDS(on) = 29mΩ @ VGS = 4.5V
•
The high-side switch (Q1) is designed with specific
emphasis on reducing switching losses while the lowside switch (Q2) is optimized to reduce conduction
losses. Q2 also includes an integrated Schottky diode
using Fairchild’s monolithic SyncFET technology.
Q1:
Optimized for low switching losses
Low Gate Charge ( 8 nC typical)
6.9A, 30V
RDS(on) = 30mΩ @ VGS = 10V
RDS(on) = 37mΩ @ VGS = 4.5V
S1D2
D
S1D2
D
S1D2
D
G1
D
1
8
Q1
2
7
3
6
Q2
4
S2
G2 G
SO-8
Pin 1
SO-
Absolute Maximum Ratings
Symbol
Dual N-Channel SyncFet
TA = 25°C unless otherwise noted
Parameter
VDSS
VGSS
ID
Q2
Drain Current
- Continuous
- Pulsed
Power Dissipation for Dual Operation
Power Dissipation for Single Operation
(Note 1a)
Units
30
±20
8.2
30
±20
6.9
20
V
V
A
2
1.6
1
0.9
–55 to +150
°C
(Note 1a)
78
°C/W
(Note 1)
40
°C/W
(Note 1a)
(Note 1b)
(Note 1c)
TJ, TSTG
Q1
30
Drain-Source Voltage
Gate-Source Voltage
PD
5
D1 S
D1 S
S
Operating and Storage Junction Temperature Range
W
Thermal Characteristics
RθJA
Thermal Resistance, Junction-to-Ambient
RθJC
Thermal Resistance, Junction-to-Case
Package Marking and Ordering Information
Device Marking
Device
Reel Size
Tape width
Quantity
FDS6900S
FDS6900S
13”
12mm
2500 units
2003 Fairchild Semiconductor Corporation
FDS6900S Rev C(W)
FDS6900S
January 2003
Symbol
(continued)
Parameter
TA = 25°C unless otherwise noted
Test Conditions
Type Min
Typ
Max Units
Drain–Source Diode Characteristics and Maximum Ratings
IS
Maximum Continuous Drain-Source Diode Forward Current
Trr
Reverse Recovery Time
Qrr
Reverse Recovery Charge
Trr
Reverse Recovery Time
IF = 8.2 A,
diF/dt = 300 A/µs
2.3
1.3
(Note 3)
17
ns
nC
ns
Q1
Qrr
Reverse Recovery Charge
VSD
Drain-Source Diode Forward VGS = 0 V, IS = 2.3 A
Voltage
VGS = 0 V, IS = 5 A
VGS = 0 V, IS = 1.3 A
(Note 2)
(Note 2)
(Note 2)
A
24
(Note 3)
IF = 6.9 A,
diF/dt = 100 A/µs
Q2
Q1
Q2
18
Q2
Q2
Q1
15
0.4
0.6
0.7
nC
0.7
1.0
1.2
V
Notes:
1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design.
a)
78°C/W when
mounted on a
2
0.5in pad of 2
oz copper
b)
125°C/W when
mounted on a
2
0.02 in pad of
2 oz copper
c)
135°C/W when
mounted on a
minimum pad.
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%
3. See “SyncFET Schottky body diode characteristics” below.
FDS6900S Rev C (W)
FDS6900S
Electrical Characteristics
