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24LC01B-TBB

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仕様・特性

24AA01/24LC01B 1K I2C™ Serial EEPROM Device Selection Table Part Number VCC Range Max. Clock Frequency 24AA01 1.7-5.5 400 kHz(1) 24LC01B 2.5-5.5 400 kHz Note 1: Description: Temp. Ranges I I, E 100 kHz for VCC <2.5V. Features: • Single Supply with Operation down to 1.7V for 24AAXX Devices, 2.5V for 24LCXX Devices • Low-Power CMOS Technology: - Read current 1 mA, max. - Standby current 1 μA, max. (I-temp) • 2-Wire Serial Interface, I2C™ Compatible • Schmitt Trigger inputs for Noise Suppression • Output Slope Control to eliminate Ground Bounce • 100 kHz and 400 kHz Compatibility • Page Write Time 3 ms, typical • Hardware Write-Protect • ESD Protection >4,000V • More than 1 Million Erase/Write Cycles • Data Retention >200 Years • Factory Programmable Available • Packages include 8-lead PDIP, SOIC, TSSOP, DFN, TDFN, MSOP, 5-lead SOT-23 and SC-70 • Pb-free and RoHS Compliant • Temperature Ranges: - Industrial (I): -40°C to +85°C - Automotive (E): -40°C to +125°C The Microchip Technology Inc. 24AA01/24LC01B (24XX01*) is a 1 Kbit Electrically Erasable PROM. The device is organized as one block of 128 x 8-bit memory with a 2-wire serial interface. Low-voltage design permits operation down to 1.7V with standby and active currents of only 1 μA and 1 mA, respectively. The 24XX01 also has a page write capability for up to 8 bytes of data. The 24XX01 is available in the standard 8-pin PDIP, surface mount SOIC, TSSOP, 2x3 DFN, 2x3 TDFN and MSOP packages, and is also available in the 5-lead SOT-23 and SC-70 packages. Package Types SOIC, TSSOP PDIP, MSOP A0 1 8 VCC A0 1 8 VCC A1 2 7 WP A1 2 7 WP A2 3 6 SCL A2 3 6 SCL VSS 4 5 SDA VSS 4 5 SDA SOT-23/SC-70 1 SCL 5 DFN/TDFN WP A0 1 A1 2 Vss 2 SDA 3 Note: A2 3 VSS 4 4 8 VCC 7 WP 6 SCL 5 SDA Vcc Pins A0, A1 and A2 are not used by the 24XX01 (no internal connections). Block Diagram WP I/O Control Logic Memory Control Logic HV Generator XDEC EEPROM Array Page Latches I/O SCL YDEC SDA VCC VSS © 2009 Microchip Technology Inc. Sense Amp. R/W Control DS21711J-page 1 24AA01/24LC01B TABLE 1-2: AC CHARACTERISTICS AC CHARACTERISTICS Param. No. Sym. Characteristic Industrial (I): TA = -40°C to +85°C, VCC = +1.7V to +5.5V Automotive (E): TA = -40°C to +125°C, VCC = +2.5V to +5.5V Min. Typ. Max. Units Conditions 1 FCLK Clock frequency — — — — 400 100 kHz 2.5V ≤ VCC ≤ 5.5V 1.7V ≤ VCC < 2.5V (24AA01) 2 THIGH Clock high time 600 4000 — — — — ns 2.5V ≤ VCC ≤ 5.5V 1.7V ≤ VCC <2.5V (24AA01) 3 TLOW Clock low time 1300 4700 — — — — ns 2.5V ≤ VCC ≤ 5.5V 1.7V ≤ VCC < 2.5V (24AA01) 4 TR SDA and SCL rise time (Note 1) — — — — 300 1000 ns 2.5V ≤ VCC ≤ 5.5V 1.7V ≤ VCC < 2.5V (24AA01) 5 TF SDA and SCL fall time — — — 300 ns (Note 1) 6 THD:STA Start condition hold time 600 4000 — — — — ns 2.5V ≤ VCC ≤ 5.5V 1.7V ≤ VCC < 2.5V (24AA01) 7 TSU:STA Start condition setup time 600 4700 — — — — ns 2.5V ≤ VCC ≤ 5.5V 1.7V ≤ VCC < 2.5V (24AA01) 8 THD:DAT Data input hold time 0 — — — ns (Note 2) 9 TSU:DAT Data input setup time 100 250 — — — — ns 2.5V ≤ VCC ≤ 5.5V 1.7V ≤ VCC < 2.5V (24AA01) 10 TSU:STO Stop condition setup time 600 4000 — — — — ns 2.5V ≤ VCC ≤ 5.5V 1.7V ≤ VCC < 2.5V (24AA01) 11 TAA Output valid from clock (Note 2) — — — — 900 3500 ns 2.5V ≤ VCC ≤ 5.5V 1.7V ≤ VCC < 2.5V (24AA01) 12 TBUF Bus free-time: Time the bus must be free before a new transmission can start 1300 4700 — — — — ns 2.5V ≤ VCC ≤ 5.5V 1.7V ≤ VCC < 2.5V (24AA01) 13 TOF Output fall time from VIH minimum to VIL maximum 20+0.1CB — — — 250 250 ns 2.5V ≤ VCC ≤ 5.5V 1.7V ≤ VCC < 2.5V (24AA01) 14 TSP Input filter spike suppression (SDA and SCL pins) — — 50 ns (Notes 1 and 3) 15 TWC Write cycle time (byte or page) — — 5 ms — 16 — Endurance 1M — — Note 1: 2: 3: 4: cycles 25°C, (Note 4) Not 100% tested. CB = total capacitance of one bus line in pF. As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation. This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site at www.microchip.com. © 2009 Microchip Technology Inc. DS21711J-page 3

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