SN74LVC2G125-Q1
DUAL BUS BUFFER GATE
WITH 3-STATE OUTPUTS
www.ti.com
SCES559A – MARCH 2004 – REVISED DECEMBER 2005
FEATURES
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(1)
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Qualification in Accordance With AEC-Q100 (1)
Qualified for Automotive Applications
Customer-Specific Configuration Control Can
Be Supported Along With Major-Change
Approval
Supports 5-V VCC Operation
Inputs Accept Voltages to 5.5 V
Max tpd of 4.3 ns at 3.3 V
Low Power Consumption, 10-µA Max ICC
±24-mA Output Drive at 3.3 V
Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
>2 V at VCC = 3.3 V, TA = 25°C
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Ioff Supports Partial-Power-Down Mode
Operation
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DCT OR DCU PACKAGE
(TOP VIEW)
1OE
1A
2Y
GND
Contact factory for details. Q100 qualification data available
on request.
1
8
2
7
3
6
4
5
VCC
2OE
1Y
2A
DESCRIPTION/ORDERING INFORMATION
The SN74LVC2G125-Q1 is a dual bus buffer gate designed for 1.65-V to 5.5-V VCC operation. This device
features dual line drivers with 3-state outputs. The outputs are disabled when the associated output-enable (OE)
input is high.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
PACKAGE (1)
TA
–40°C to 85°C
(1)
(2)
(3)
ORDERABLE PART NUMBER
TOP-SIDE MARKING (2)
SSOP – DCT
Tape and reel
SN74LVC2G125IDCTRQ1
C25_ _ _
VSSOP – DCU
Tape and reel
SN74LVC2G125IDCURQ1 (3)
C25_
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.
DCU: The actual top-side marking has one additional character that designates the assembly/test site.
Product preview
FUNCTION TABLE
(EACH BUFFER)
INPUTS
OE
A
OUTPUT
Y
L
H
H
L
L
L
H
X
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2005, Texas Instruments Incorporated
SN74LVC2G125-Q1
DUAL BUS BUFFER GATE
WITH 3-STATE OUTPUTS
www.ti.com
SCES559A – MARCH 2004 – REVISED DECEMBER 2005
Recommended Operating Conditions
(1)
MIN
VCC
Supply voltage
Operating
Data retention only
VCC = 1.65 V to 1.95 V
VIH
High-level input voltage
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
MAX
1.65
5.5
1.5
Low-level input voltage
1.7
0.7 × VCC
0.35 × VCC
VCC = 2.3 V to 2.7 V
0.7
VCC = 3 V to 3.6 V
0.8
Input voltage
VO
Output voltage
0
5.5
High or low state
0
VCC
3-state
0
5.5
VCC = 3 V
–32
4
VCC = 2.3 V
8
16
VCC = 3 V
32
VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V
Input transition rise or fall rate
20
VCC = 3.3 V ± 0.3 V
10
VCC = 5 V ± 0.5 V
TA
(1)
Operating free-air temperature
mA
24
VCC = 4.5 V
∆t/∆v
mA
–24
VCC = 1.65 V
Low-level output current
V
–8
–16
VCC = 4.5 V
IOL
V
–4
VCC = 2.3 V
High-level output current
V
0.3 × VCC
VCC = 1.65 V
IOH
V
2
VCC = 4.5 V to 5.5 V
VI
V
0.65 × VCC
VCC = 1.65 V to 1.95 V
VIL
UNIT
ns/V
5
–40
85
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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