HM628128B Series
1 M SRAM (128-kword × 8-bit)
ADE-203-243E (Z)
Rev. 5.0
Nov. 1997
Description
The Hitachi HM628128B is a CMOS static RAM organized 131,072-word × 8-bit. It realizes higher
density, higher performance and low power consumption by employing 0.8 µm Hi-CMOS shrink process
technology. It offers low power standby power dissipation, therefore, it is suitable for battery backup
systems. The device, packaged in a 525 mil SOP or a 8 mm × 20 mm TSOP or a 600 mil plastic DIP is
available.
Features
• Single 5 V supply: 5.0 V ± 10%
• Access time: 70/75/85 ns (max)
• Power dissipation
Active: 50 mW/MHz (typ)
Standby: 10 µW (typ) (L/L-SL version)
• Completely static memory
No clock or timing strobe required
• Equal access and cycle times
• Common data input and output
Three state output
• Directly TTL compatible all inputs and outputs
• Capability of battery backup operation (L/L-SL version)
2 chip selection for battery backup
HM628128B Series
Pin Arrangement
HM628128BT Series (Normal Type TSOP)
HM628128BP/BFP Series
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
1
32
2
31
3
30
4
29
5
28
6
27
7
26
8
25
9
24
10
23
11
22
12
21
13
20
14
19
15
18
16
17
VCC
A15
CS2
WE
A13
A8
A9
A11
OE
A10
CS1
I/O7
I/O6
I/O5
I/O4
I/O3
(Top view)
A11
A9
A8
A13
WE
CS2
A15
VCC
NC
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CS1
I/O7
I/O6
I/O5
I/O4
I/O3
VSS
I/O2
I/O1
I/O0
A0
A1
A2
A3
(Top view)
HM628128BR Series (Reverse Type TSOP)
A4
A5
A6
A7
A12
A14
A16
NC
VCC
A15
CS2
WE
A13
A8
A9
A11
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
I/O3
I/O4
I/O5
I/O6
I/O7
CS1
A10
OE
(Top View)
Pin Description
Pin name
Function
A0 to A16
Address input
I/O0 to I/O7
Data input/output
CS1
Chip select 1
CS2
Chip select 2
WE
Write enable
OE
Output enable
NC
No connection
VCC
Power supply
VSS
Ground
3
