ICS9112-16
Integrated
Circuit
Systems, Inc.
Preliminary Product Preview
Low Skew Output Buffer
General Description
Features
The ICS9112-16 is a high performance, low skew, low jitter
clock driver. It uses a phase lock loop (PLL) technology to
align, in both phase and frequency, the REF input with the
CLKOUT signal. It is designed to distribute high speed
clocks in PC systems operating at speeds from 25 to
133 MHz.
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ICS9112-16 is a zero delay buffer that provides
synchronization between the input and output. The
synchronization is established via CLKOUT feed back to the
input of the PLL. Since the skew between the input and
output is less than +/- 350 pS, the part acts as a zero delay
buffer.
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Zero input - output delay
Frequency range 25 - 133 MHz (3.3V)
High loop filter bandwidth ideal for Spread
Spectrum applications.
Less than 200 ps Jitter between outputs
Skew controlled outputs
Skew less than 250 ps between outputs
Available in 8 pin 150 mil SOIC package
3.3V ±10% operation
The ICS9112-16 comes in an eight pin 150 mil SOIC package.
It has five output clocks. In the absence of REF input, will be
in the power down mode. In this mode, the PLL is turned off
and the output buffers are pulled low. Power down mode
provides the lowest power consumption for a standby
condition.
Block Diagram
Pin Configuration
8 pin SOIC
9112-16 Rev D 4/14/99
PRODUCT PREVIEW documents contain information on new
products in the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change
without notice.
