MT9042B
®
Multitrunk System Synchronizer
Preliminary Information
Features
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ISSUE 1
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Ordering Information
Meets jitter requirements for AT&T TR62411
Stratum 3, 4 and Stratum 4 Enhanced for DS1
interfaces and for ETSI ETS 300 011 for E1
interfaces
Provides C1.5, C3, C2, C4, C8 and C16 output
clock signals
Provides 8kHz ST-BUS framing signals
Selectable 1.544MHz, 2.048MHz or 8kHz input
reference signals
Accepts reference inputs from two independent
sources
Provides bit error free reference switching meets phase slope and MTIE requirements
Operates in either Normal, Holdover and
Freerun modes
MT9042BP
28 Pin PLCC
-40°C to +85 ° C
d
de
Description
enign
The MT9042B
Synchronizer
mmes 2C digital Multitrunk System (DPLL), which
contains a
phase-locked loop
cow D provides timing E1 primary rate transmission links.
and synchronization signals for
04
e e
multitrunk T1 and
9
t Rr N MT
The MT9042B generates ST-BUS clock and framing
No fo ee
signals that are phase locked to either a 2.048MHz,
S
1.544MHz, or 8kHz input reference.
The MT9042B is compliant with AT&T TR62411
Stratum 3, 4 and 4 Enhanced, and ETSI ETS 300
011. It will meet the jitter tolerance, jitter transfer,
intrinsic jitter, frequency accuracy, holdover
accuracy, capture range, phase slope and MTIE
requirements for these specifications.
Applications
•
October 1996
Synchronization and timing control for
multitrunk T1 and E1 systems
ST-BUS clock and frame pulse sources
Primary Trunk Rate Converters
TRST
OSCi
TIE
Corrector
Circuit
Master
Clock
OSCo
PRI
SEC
Reference
Select
TIE
Corrector
Enable
Automatic/Manual
Control State Machine
MS1
MS2
RST
VSS
Virtual
Reference
DPLL
Output
Interface
Circuit
Selected
Reference
Reference
Select
MUX
RSEL
LOS1
LOS2
VDD
State
Select
State
Select
Input
Impairment
Monitor
C1.5o
C3o
C2o
C4o
C8o
C16o
F0o
F8o
F16o
Feedback
Guard Time
Circuit
GTo
GTi
Frequency
Select
MUX
FS1
FS2
Figure 1 - Functional Block Diagram
3-97
