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BUK564-60H
Philips Semiconductors Product specification PowerMOS transistor Logic level FET GENERAL DESCRIPTION N-channel enhancement mode logic level field-effect power transistor in a plastic envelope suitable for surface mount applications. The device is intended for use in automotive and general purpose switching applications. PINNING - SOT404 PIN BUK564-60H QUICK REFERENCE DATA SYMBOL PARAMETER VDS ID Ptot Tj RDS(ON) Drain-source voltage Drain current (DC) Total power dissipation Junction temperature Drain-source on-state resistance; VGS = 5 V PIN CONFIGURATION MAX. UNIT 60 39 125 175 42 V A W ˚C mΩ SYMBOL DESCRIPTION d mb 1 gate 2 drain 3 source g mb drain 2 1 s 3 LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER CONDITIONS VDS VDGR ±VGS ±VGSM Drain-source voltage Drain-gate voltage Gate-source voltage Non-repetitive gate-source voltage Drain current (DC) Drain current (DC) Drain current (pulse peak value) Total power dissipation Storage temperature Junction temperature ID ID IDM Ptot Tstg Tj MIN. MAX. UNIT RGS = 20 kΩ tp ≤ 50 µs - 60 60 15 20 V V V V Tmb = 25 ˚C Tmb = 100 ˚C Tmb = 25 ˚C Tmb = 25 ˚C - - 55 - 39 28 156 125 175 175 A A A W ˚C ˚C THERMAL RESISTANCES SYMBOL PARAMETER Rth j-mb Thermal resistance junction to mounting base Thermal resistance junction to ambient Rth j-a August 1996 CONDITIONS 1 MAX. UNIT Minimum footprint, FR4 board TYP. 1.2 K/W 50 - K/W Rev 1.000
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