256Mb: x4, x8, x16 SDRAM
Features
SDR SDRAM
MT48LC64M4A2 – 16 Meg x 4 x 4 banks
MT48LC32M8A2 – 8 Meg x 8 x 4 banks
MT48LC16M16A2 – 4 Meg x 16 x 4 banks
Features
Options
• Configurations
– 64 Meg x 4 (16 Meg x 4 x 4 banks)
– 32 Meg x 8 (8 Meg x 8 x 4 banks)
– 16 Meg x 16 (4 Meg x 16 x 4 banks)
• Write recovery (tWR)
– tWR = 2 CLK1
• Plastic package – OCPL2
– 54-pin TSOP II OCPL2 (400 mil)
(standard)
– 54-pin TSOP II OCPL2 (400 mil)
Pb-free
– 60-ball FBGA (x4, x8) (8mm x 16mm)
– 60-ball FBGA (x4, x8) (8mm x 16mm)
Pb-free
– 54-ball VFBGA (x16) (8mm x 14 mm)
– 54-ball VFBGA (x16) (8mm x 14 mm)
Pb-free
• Timing – cycle time
– 6ns @ CL = 3 (x8, x16 only)
– 7.5ns @ CL = 3 (PC133)
– 7.5ns @ CL = 2 (PC133)
• Self refresh
– Standard
– Low power
• Operating temperature range
– Commercial (0˚C to +70˚C)
– Industrial (–40˚C to +85˚C)
– Automotive (–40˚C to +105˚C)
• Revision
• PC100- and PC133-compliant
• Fully synchronous; all signals registered on positive
edge of system clock
• Internal, pipelined operation; column address can
be changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto precharge, includes concurrent auto precharge and auto refresh modes
• Self refresh mode (not available on AT devices)
• Auto refresh
– 64ms, 8192-cycle (commercial and industrial)
– 16ms, 8192-cycle (automotive)
• LVTTL-compatible inputs and outputs
• Single +3.3V ±0.3V power supply
Table 1: Address Table
Parameter
64 Meg x 4 32 Meg x 8
Configuration
16 Meg x 4
x 4 banks
Refresh count
8 Meg x 8 x
4 banks
16 Meg
x 16
4 Meg x 16
x 4 banks
8K
8K
8K
Row addressing
8K A[12:0]
8K A[12:0]
8K A[12:0]
Bank addressing
4 BA[1:0]
4 BA[1:0]
4 BA[1:0]
Column
addressing
2K A[9:0],
A11
1K A[9:0]
512 A[8:0]
Notes:
Table 2: Key Timing Parameters
CL = CAS (READ) latency
Access Time
Speed
Grade
Clock
Frequency
Setup
Time
-6A
167 MHz
–
1.5ns
-7E
143 MHz
-75
133 MHz
5.4ns
1.5ns
5.4ns
1.5ns
-7E
5.4ns
–
1.5ns
-75
6ns
–
1.5ns
FB
BB
FG
BG
-6A
-75
-7E
None
L3
None
IT
AT3
:D
1. See Micron technical note TN-48-05 on
Micron's Web site.
2. Off-center parting line.
3. Contact Micron for availability.
0.8ns
100 MHz
P
0.8ns
133 MHz
TG
0.8ns
–
A2
0.8ns
–
64M4
32M8
16M16
Hold
Time
5.4ns
Marking
0.8ns
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. N 1/10 EN
CL = 2 CL = 3
1
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 1999 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
