ETC5064/64-X
ETC5067/67-X
®
SERIAL INTERFACE CODEC/FILTER WITH RECEIVE
POWER AMPLIFIER
.
COMPLETE CODEC AND FILTERING SYSTEM INCLUDING :
- Transmit high-pass and low-pass filtering.
- Receive low-pass filter with sin x/x correction.
- Active RC noise filter.
- µ-law or A-law compatible CODER and DECODER.
- Internal precision voltage reference.
- Serial I/O interface.
- Internal auto-zero circuitry.
- Receive push-pull power amplifiers.
µ-LAW ETC5064
A-LAW ETC5067
MEETS OR EXCEEDS ALL D3/D4 AND CCITT
SPECIFICATIONS.
± 5 V OPERATION.
LOW OPERATING POWER-TYPICALLY 70 mW
POWER-DOWN STANDBY MODE-TYPICALLY
3 mW
AUTOMATIC POWER DOWN
TTL OR CMOS COMPATIBLE DIGITAL INTERFACES
MAXIMIZES LINE INTERFACE CARD CIRCUIT DENSITY
0°C TO 70°C OPERATION: ETC5064/67
–40°C TO 85°C OPERATION: ETC5064-X/67-X
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DIP20
(Plastic) N
ORDERING NUMBERS:
ETC5064N
ETC5064N-X
ETC5067N
ETC5067N-X
PLCC20
FN
ORDERING NUMBERS:
ETC5064FN
ETC5064FN-X
ETC5067FN
ETC5067FN-X
DESCRIPTION
The ETC5064 (µ-law), ETC5067 (A-law) are monolithic PCM CODEC/FILTERS utilizing the A/D and
D/A conversion architecture shown in the Block Diagrams and a serial PCM interface. The devices are
fabricated using double-poly CMOS process.
Similar to the ETC505X family, these devices feature an additional Receive Power Amplifier to provide push-pull balanced output drive capability. The
receive gain can be adjusted by means of two external resistors for an output level of up to ± 6.6 V
across a balanced 600Ω load.
Also included is an Analog Loopback switch and
TSX output.
September 2003
SO20
D
ORDERING NUMBERS:
ETC5064D
ETC5064D-X
ETC5067D
ETC5067D-X
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ETC5064 - ETC5064-X - ETC5067 - ETC5067-X
PIN DESCRIPTION
Name
+
Pin
Type (*)
N
Description
O
1
The Non-inverting Output of the Receive Power Amplifier
GND
2
Analog Ground. All signals are referenced to this pin.
VPOVPI
O
3
The Inverting Output of the Receive Power Amplifier
I
4
Inverting Input to the Receive Power Amplifier. Also powers down both
amplifiers when connected to VBB.
VFRO
O
5
Analog Output of the Receive Filter.
VCC
S
6
Positive Power Supply Pin. VCC = +5V ±5%
FSR
I
7
Receive Frame Sync Pulse which enable BCLKR to shift PCM data into
DR. FSR is an 8KHz pulse train. See figures 1 and 2 for timing details.
DR
I
8
Receive Data Input. PCM data is shifted into DR following the FSR leading
edge
BCLKR/CLKSEL
I
9
The bit Clock which shifts data into DR after the FSR leading edge. May
vary from 64KHz to 2.048MHz.
Alternatively, may be a logic input which selects either 1.536MHz/1.544MHz
or 2.048MHz for master clock in synchronous mode and BCLK X is used
for both transmit and receive directions (see table 1). This input has an
internal pull-up.
MCKLR/PDN
I
10
Receive Master Clock. Must be 1.536MHz, 1.544MHz or 2.048MHz. May
be asynchronous with MCLKX, but should be synchronous with MCLKX for
best performance. When MCLKR is connected continuously low, MCLKX is
selected for all internal timing. When MCLKR is connected continuously
high, the device is powered down.
MCLKX
I
11
Transmit Master Clock. Must be 1.536MHz, 1.544MHz or 2.048MHz. May
be asynchronous with MCLKR.
BCLKX
I
12
The bit clock which shifts out the PCM data on DX. May vary from 64KHz
to 2.048MHz, but must be synchronous with MCLKX.
DX
O
13
FSX
I
14
The TRI-STATE®PCM data output which is enabled by FSX.
Transmit frame sync pulse input which enables BCLKX to shift out the
PCM data on DX. FSX is an 8KHz pulse train. See figures 1 and 2 for
timing details.
TSX
O
15
ANLB
I
16
Open drain output which pulses low during the encoder time slot. Must to
be grounded if not used.
Analog Loopback Control Input. Must be set to logic ’0’ for normal
operation. When pulled to logic ’1’, the transmit filter input is disconnected
from the output of the transmit preamplifier and connected to the VPO +
output of the receive power amplifier.
GSX
VFXI-
O
I
17
18
Analog output of the transmit input amplifier. Used to set gain externally.
Inverting input of the transmit input amplifier.
VFXI+
VBB
I
S
19
20
Negative Power Supply Pin. VBB = -5V ±5%
VPO
GNDA
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- O let
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t(s
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Non-inverting input of the transmit input amplifier.
(*) I: Input, O: Output, S: Power Supply.
TRI-STATE® is a trademark of National Semiconductor Corp.
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