CDC303
OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER
SCAS323A – JULY 1990 – REVISED NOVEMBER 1995
D
D
D
D
D
D
D OR N PACKAGE
(TOP VIEW)
Replaces SN74AS303
Maximum Output Skew Between Same
Phase Outputs of 1 ns
Maximum Pulse Skew of 1 ns
TTL-Compatible Inputs and Outputs
Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise
Package Options Include Plastic
Small-Outline (D) Package and Standard
Plastic (N) 300-mil DIPs
Q3
Q4
GND
GND
GND
Q5
Q6
Q7
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
Q2
Q1
CLR
VCC
VCC
CLK
PRE
Q8
description
The CDC303 contains eight flip-flops designed to have low skew between outputs. The eight outputs (six
in-phase with CLK and two out-of-phase) toggle on successive CLK pulses. Preset (PRE) and clear (CLR)
inputs are provided to set the Q and Q outputs high or low independent of the clock (CLK) input.
The CDC303 has output and pulse-skew parameters tsk(o) and tsk(p) to ensure performance as a clock driver
when a divide-by-two function is required.
The CDC303 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS
OUTPUTS
CLR
PRE
CLK
Q1– Q6
Q7– Q8
L
H
X
L
H
H
L
X
L
L
X
H
L†
L
L†
H
H
↑
Q0
Q0
H
H
L
Q0
Q0
† This configuration does not persist when
PRE or CLR returns to its inactive (high)
level.
logic symbol‡
15
16
PRE
10
1
S
2
CLK
11
6
T
7
CLR
14
Q1
Q2
Q3
Q4
Q5
Q6
8
R
9
Q7
Q8
‡ This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
CDC303
OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER
SCAS323A – JULY 1990 – REVISED NOVEMBER 1995
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VOH
VOL
II
IIH
IIL
IO‡
TEST CONDITIONS
MIN
VCC = 4.5 V,
VCC = 4.5 V to 5.5 V,
IOH = – 24 mA
IOL = 48 mA
VCC = 5.5 V,
VCC = 5.5 V,
VI = 7 V
VI = 2.7 V
VCC = 5.5 V,
VCC = 5.5 V,
VI = 0.4 V
VO = 2.25 V
VCC – 2
2
MAX
UNIT
– 1.2
II = – 18 mA
IOH = – 2 mA
VCC = 4.5 V,
VCC = 4.5 V,
TYP†
V
V
2.8
0.3
0.5
V
0.1
mA
20
mA
– 150
– 50
µA
– 0.5
mA
ICC
VCC = 5.5 V,
See Note 2
40
70
mA
† All typical values are at VCC = 5 V, TA = 25°C.
‡ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
NOTE 2: ICC is measured with CLK and PRE grounded, then with CLK and CLR grounded.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
MIN
fclock
MAX
UNIT
0
Clock frequency
80
MHz
CLR or PRE low
tw
Pulse duration
5
tsu
CLK high
6
CLR or PRE inactive
Setup time before CLK↑
ns
4
CLK low
6
ns
switching characteristics over recommended operating free-air temperature range (see Figure 1)
PARAMETER
fmax§
tPLH
tPHL
tPLH
tPHL
FROM
(INPUT)
TO
(OUTPUT)
CLK
Q,
Q Q
RL = 500 Ω
Ω,
CL = 50 pF
PRE or CLR
Q,
Q Q
RL = 500 Ω
Ω,
CL = 50 pF
RL = 500 Ω
Ω,
See Figure 2
CL = 10 pF to 30 pF,
Ft
F
MAX
CLK
Q
CLK
Q, Q
UNIT
MHz
2
9
2
9
3
12
3
12
ns
ns
1
Q, Q
tsk(p)
MIN
80
Q
tsk(o)
( )
TEST CONDITIONS
1
ns
2
RL = 500 Ω,
CL = 10 pF to 30 pF
1
ns
4.5
ns
3.5
tr
tf
ns
§ fmax minimum values are at CL = 0 to 30 pF.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
