CY7C64713
EZ-USB FX1™ USB Microcontroller
Full Speed USB Peripheral Controller
Features
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Integrated, Industry Standard 8051 with Enhanced Features:
Single Chip Integrated USB Transceiver, SIE, and Enhanced
8051 Microprocessor
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Up to 48 MHz clock rate
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Four clocks for each instruction cycle
Fit, Form, and Function Upgradable to the FX2LP
(CY7C68013A)
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Two USARTS
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Three counters or timers
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Expanded interrupt system
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Two data pointers
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Pin compatible
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Object code compatible
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Functionally compatible (FX1 functionality is a Subset of the
FX2LP)
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3.3V Operation with 5V Tolerant Inputs
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Draws No More than 65 mA in Any Mode, Making the FX1
Suitable for Bus Powered Applications
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Smart SIE
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Vectored USB Interrupts
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Software: 8051 Runs from Internal RAM, which is:
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Separate Data Buffers for the Setup and DATA Portions of a
CONTROL Transfer
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Downloaded using USB
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Loaded from EEPROM
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Integrated I2C Controller, Running at 100 or 400 KHz
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External memory device (128 pin configuration only)
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48 MHz, 24 MHz, or 12 MHz 8051 Operation
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Four Integrated FIFOs
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16 KBytes of On-Chip Code/Data RAM
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Four Programmable BULK/INTERRUPT/ISOCHRONOUS
Endpoints
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Buffering options: double, triple, and quad
Brings glue and FIFOs inside for lower system cost
Automatic conversion to and from 16-bit buses
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Master or slave operation
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Additional Programmable (BULK/INTERRUPT) 64-byte
Endpoint
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FIFOs can use externally supplied clock or asynchronous
strobes
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8- or 16-bit External Data Interface
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Easy interface to ASIC and DSP ICs
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Smart Media Standard ECC Generation
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Vectored for FIFO and GPIF Interrupts
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GPIF
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Up to 40 General Purpose IOs (GPIO)
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Four Package Options:
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Allows direct connection to most parallel interfaces; 8- and
16-bit
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Programmable waveform descriptors and configuration
registers to define waveforms
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Supports multiple Ready (RDY) inputs and Control (CTL)
outputs
Cypress Semiconductor Corporation
Document #: 38-08039 Rev. *G
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198 Champion Court
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128 pin TQFP
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100 pin TQFP
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56 pin SSOP
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56 pin QFN Pb-free
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San Jose, CA 95134-1709
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408-943-2600
Revised September 15, 2009
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