TC358764XBG/TC358765XBG
CMOS Digital Integrated Circuit Silicon Monolithic
TC358764XBG/TC358765XBG
Mobile Peripheral Devices
TC358764XBG
Overview
The primary function of TC358764XBG/TC358765XBG is DSI-to-LVDS
Bridge, enabling video streaming output over DSI link to drive
LVDS-compatible display panels. The chip supports up to 1366×768
24-bit pixel resolution for single-link LVDS and up to WUXGA (1920x1200
18-bit pixels) resolution for dual-link LVDS. As a secondary function, the
chip also supports an I2C Master which is controlled by the DSI link; this
may be used as an interface to any other control functions through I2C.
The chip can be configured through the DSI link by sending write register
commands through DSI Generic Long Write-packets. It can also be
configured through the I2C Slave interface.
● DSI Receiver
Configurable 1- up to 4-Data-Lane DSI Link with
bi-directional support on Data Lane 0
Maximum bit rate of 800 Mbps/lane
Video input data formats:
- RGB565 16 bits per pixel
- RGB666 18 bits per pixel
- RGB666 loosely packed 24 bits per pixel
- RGB888 24 bits per pixel.
Video frame size:
- Up to 1366×768 24-bit/pixel resolution to
single-link LVDS display panel
- Up to WUXGA resolutions (1920×1200 18-bit
pixels) to dual-link LVDS display panel
Supports Video Stream packets for video data
transmission.
Supports generic long packets for accessing the
chip’s register set
Supports the path for Host to control the on-chip I2C
Master
© 2014 Toshiba Corporation
TC358765XBG
P-TFBGA64-0606-0.65AZ
Weight: 74.7 mg (Typ.)
Features
● LVDS FPD Link Transmitter
Supports single-link or dual-link
Maximum pixel clock frequency of 85 MHz
Maximum throughput of 297.5 MBytes/sec for
single-link or 595 Mbytes/sec for dual-link
Supports display up to 1366×768 24-bit/pixel
resolution for single-link, or up to WUXGA (18
bit/pixel) resolutions for dual-link
Supports the following pixel formats:
- RGB666 18 bits per pixel
- RGB888 24 bits per pixel
Features Toshiba Magic Square algorithm which
enables a RGB666 display panel to produce a
display quality equivalent to that of an RGB888
24-bit panel
Flexible mapping of parallel data input bit ordering
P-TFBGA49-0505-0.65AZ
Weight: 53.8 mg (Typ.)
Supports programmable clock polarity
Supports power-down
● System Operation
Host configures the chip through DSI link
Through DSI link, Host accesses the chip register set
using Generic Write and Read packets. One Generic
Long Write packet can write to multiple contiguous
register addresses
Includes an I2C Master function which is controlled
by Host through DSI link (multi-master is not
supported)
Power management features to save power
Configuration registers is also accessible through
I2C Slave interface
● Clock Source
LVDS pixel clock source is either from external
clock EXTCLK or derived from DSICLK.
A built-in PLL generates the high-speed LVDS
serializing clock requiring no external components
● Digital Input/Output Signals
All Digital Input signals are 3.3V tolerant
All Digital Output signals can output ranging from
1.8V to 3.3V depending on IO supply voltage
● Power supply
MIPI DSI D-PHY: 1.2 V
LVDS PHY: 3.3 V
I/O:
1.8 V - 3.3V (all IO supply pins must
be same level)
Digital Core: 1.2 V
● Power Consumption
Power –down mode is achieved by:
1. Disable PLL (0x04A0[8] = 1) and LVDS
(0x049C[0] = 0) after stopping video stream (in
DSI LP11 state)
2. Drive DSI Data Lanes to LP00 state
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2014-05-29
