Product Obsolete or Under Obsolescence 0 XC3000 Series Field Programmable Gate Arrays (XC3000A/L, XC3100A/L) R November 9, 1998 (Version 3.1) 0 7* Features • • • • • • • • Complete line of four related Field Programmable Gate Array product families - XC3000A, XC3000L, XC3100A, XC3100L Ideal for a wide range of custom VLSI design tasks - Replaces TTL, MSI, and other PLD logic - Integrates complete sub-systems into a single package - Avoids the NRE, time delay, and risk of conventional masked gate arrays High-performance CMOS static memory technology - Guaranteed toggle rates of 70 to 370 MHz, logic delays from 7 to 1.5 ns - System clock speeds over 85 MHz - Low quiescent and active power consumption Flexible FPGA architecture - Compatible arrays ranging from 1,000 to 7,500 gate complexity - Extensive register, combinatorial, and I/O capabilities - High fan-out signal distribution, low-skew clock nets - Internal 3-state bus capabilities - TTL or CMOS input thresholds - On-chip crystal oscillator amplifier Unlimited reprogrammability - Easy design iteration - In-system logic changes Extensive packaging options - Over 20 different packages - Plastic and ceramic surface-mount and pin-gridarray packages - Thin and Very Thin Quad Flat Pack (TQFP and VQFP) options Ready for volume production - Standard, off-the-shelf product availability - 100% factory pre-tested devices - Excellent reliability record Device XC3020A, 3020L, 3120A XC3030A, 3030L, 3130A XC3042A, 3042L, 3142A, 3142L Product Description Max Logic Gates 1,500 2,000 3,000 Additional XC3100A Features • • • • • • Ultra-high-speed FPGA family with six members - 50-85 MHz system clock rates - 190 to 370 MHz guaranteed flip-flop toggle rates - 1.55 to 4.1 ns logic delays High-end additional family member in the 22 X 22 CLB array-size XC3195A device 8 mA output sink current and 8 mA source current Maximum power-down and quiescent current is 5 mA 100% architecture and pin-out compatible with other XC3000 families Software and bitstream compatible with the XC3000, XC3000A, and XC3000L families XC3100A combines the features of the XC3000A and XC3100 families: • • • • Additional interconnect resources for TBUFs and CE inputs Error checking of the configuration bitstream Soft startup holds all outputs slew-rate limited during initial power-up More advanced CMOS process Low-Voltage Versions Available • • • Typical Gate CLBs Range 1,000 - 1,500 64 1,500 - 2,000 2,000 - 3,000 Complete Development System - Schematic capture, automatic place and route - Logic and timing simulation - Interactive design editor for design optimization - Timing calculator - Interfaces to popular design environments like Viewlogic, Cadence, Mentor Graphics, and others 100 144 Low-voltage devices function at 3.0 - 3.6 V XC3000L - Low-voltage versions of XC3000A devices XC3100L - Low-voltage versions of XC3100A devices Array 8x8 10 x 10 12 x 12 User I/Os Flip-Flops Max 64 256 80 96 360 480 Horizontal Longlines 16 Configuration Data Bits 14,779 20 24 22,176 30,784 XC3064A, 3064L, 3164A 4,500 3,500 - 4,500 224 16 x 14 120 688 32 46,064 XC3090A, 3090L, 3190A, 3190L XC3195A 6,000 7,500 5,000 - 6,000 6,500 - 7,500 320 484 16 x 20 22 x 22 144 176 928 1,320 40 44 64,160 94,984 November 9, 1998 (Version 3.1) 7-3 7 Product Obsolete or Under Obsolescence R XC3000 Series Field Programmable Gate Arrays Improvements in the XC3000A and XC3000L Families nality Functio The XC3000A and XC3000L families offer the following enhancements over the popular XC3000 family: The XC3000A and XC3000L families have additional interconnect resources to drive the I-inputs of TBUFs driving horizontal Longlines. The CLB Clock Enable input can be driven from a second vertical Longline. These two additions result in more efficient and faster designs when horizontal Longlines are used for data bussing. 0A XC310 00L 0 XC310XC31 0A XC300 0L XC300 Speed During configuration, the XC3000A and XC3000L devices check the bit-stream format for stop bits in the appropriate positions. Any error terminates the configuration and pulls INIT Low. When the configuration process is finished and the device starts up in user mode, the first activation of the outputs is automatically slew-rate limited. This feature, called Soft Startup, avoids the potential ground bounce when all out-puts are turned on simultaneously. After start-up, the slew rate of the individual outputs is, as in the XC3000 family, determined by the individual configuration option. ) 195A (XC3 city Capa Gate X7068 Figure 1: XC3000 FPGA Families Improvements in the XC3100A and XC3100L Families 7 Based on a more advanced CMOS process, the XC3100A and XC3100L families are architecturally-identical, performance-optimized relatives of the XC3000A and XC3000L families. While all families are footprint compatible, the XC3100A family extends achievable system performance beyond 85 MHz. November 9, 1998 (Version 3.1) 7-5




Xilinx, Inc






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