DATA SHEET
BIPOLAR ANALOG INTEGRATED CIRCUIT
µPC4091
J-FET INPUT LOW-OFFSET OPERATIONAL AMPLIFIER
The µPC4091 operational amplifier offers high input impedance, low offset voltage, high slew rate, and stable AC
operating characteristics. NEC's unique high-speed PNP transistor (fT = 300 MHz) in the output stage solves the
oscillation problem of current sinking with a large capacitive load. Zener-zap resistor trimming in the input stage
produces excellent offset voltage and temperature drift characteristics.
FEATURES
• Stable operation with 10000 pF capacitive load
• Low noise : en = 19 nV/ √Hz (TYP.)
• Low input offset voltage and offset voltage null
• Output short circuit protection
capability
• High input impedance ... J-FET Input Stage
±2.5 mV (MAX.)
• Internal frequency compensation
±7 µV/°C (TYP.) temperature drift
• High slew rate: 15 V/µs (TYP.)
• Very low input bias and offset currents
ORDERING INFORMATION
Part Number
Package
µPC4091C
8-pin plastic DIP (300 mil)
µPC4091G2
8-pin plastic SOP (225 mil)
EQUIVALENT CIRCUIT
PIN CONFIGURATION
(Top View)
V+
(7)
µ PC4091C, 4091G2
OFFSET
1
NULL
Q9
(2)
II
Q1
Q3
Q4
TRIMMED
(5)
OFFSET
NULL
D1
IN
3
7 V+
2
4
(6)
C1
Q5
OFFSET
NULL
OUT
Q7
II
V–
Q2
IN
(3)
(1)
8 NC
Q6
Q10
HIGH SPEED
PNP
– +
6 OUT
OFFSET
5 NULL
Q8
(4)
V–
Remark NC : No Connection
The information in this document is subject to change without notice.
Document No. G13904EJ1V0DS00 (1st edition)
Date Published November 1998 N CP(K)
Printed in Japan
©
1998
