DATA SHEET
128M bits DDR SDRAM
EDD1232AABH (4M words × 32 bits)
Features
• Density: 128M bits
• Organization
1M words × 32 bits × 4 banks
• Package: 144-ball FBGA
Lead-free (RoHS compliant)
• Power supply: VDD, VDDQ = 2.5V ± 0.2V
• Data rate: 333Mbps/266Mbps (max.)
• Four internal banks for concurrent operation
• Interface: SSTL_2
• Burst lengths (BL): 2, 4, 8
• Burst type (BT):
Sequential (2, 4, 8)
Interleave (2, 4, 8)
• /CAS Latency (CL): 2, 2.5, 3
• Precharge: auto precharge operation for each burst
access
• Driver strength: half/weak
• Refresh: auto-refresh, self-refresh
• ×32 organization
• Double-data-rate architecture; two data transfers per
clock cycle
• The high-speed data transfer is realized by the 2 bits
prefetch pipelined architecture
• Bi-directional data strobe (DQS) is transmitted
/received with data for capturing data at the receiver
• Data inputs, outputs, and DM are synchronized with
DQS
• DQS is edge-aligned with data for READs; centeraligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK
transitions
• Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
• Data mask (DM) for write data
L
EO
Specifications
Pr
• Refresh cycles: 4096 cycles/32ms
Average refresh period: 7.8µs
• Operating ambient temperature range
TA = 0°C to +70°C
t
uc
od
This Product became EOL in November, 2006.
Document No. E0533E60 (Ver. 6.0)
Date Published December 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2004-2005
