Datasheet
Brief
75P42100
IP Co-Processor
32K x 72 Entries
To request the full IDT75P42100 datasheet, please contact your local
IDT Sales Representative or call 1-831-754-4555
Device Description
Block Diagram
IDT’s 75P42100 IPC is a high performance pipelined low-power,
synchronous full-ternary 32K x 72 entry device. Each entry location in
the IPC has both a Data entry and an associated Mask entry. IDT’s IPC
devices integrate content addressable memory (CAM) technology with
high-performance logic. The device can perform Lookup and Learn IPC
operations plus Read, Write, Burst Write, and Dual Write maintenance
operations.
The IDT 75P42100 IPC device has a bi-directional bus that is a
multiplexed address and data bus that can support 100 million sustained
searches per second. This device provides array segments which can
be configured to enable multiple width lookups from 36 to 576 bits wide.
The IDT 75P42100 requires a 1.8-volt VDD supply, a user selectable 1.8
or 2.5-volt VDDQ supply, and a 2.5-volt VBIAS supply. This IPC device
provides the user with flexibility and control in determining the device
power. Only the array segments that will be used for a specific IPC
operation are powered up while the unused segments are not.
The IDT 75P42100 utilizes IDT’s latest high-performance 1.8V
CMOS processing technology and is packaged in a JEDEC Standard,
thermally enhanced, low profile Ball Grid Array. The options include a
304 BGA, satisfying smaller footprint requirements and a 372 BGA
package that is compatible with IDT's 64K x 72 Entry (75P52100) and
128K x 72 Entry (75K62100) IPC devices.
LAST IPC
LAST SRAM
CLOCK
Configuration Registers
and
Ram Control Circuits
÷2
Counter
S
I
Z
E
RESET
ARRAY
REQSTB
R/W
Command
Bus
L
O
G
I
C
Instruction
IPC
REQUEST
BUS
D
E
Request
Data
Bus
ASIC FEEDBACK
CCLK
PHASE
BURST
SRAM CONTROL
C
Address
O
D
E
P
R
I
O
R
I
T
Y
Index
Bus
IPC
RESPONSE
BUS
E
N
C
O
D
E
R
Bypass
Comparand Registers
MMOUT
Global Mask Registers
DATA
MATCHOUT
Result Register
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Features
System Configurations
x
IDT’s IPCs are designed to fulfill the needs of various types of
networking systems. In solutions requiring data searching such as
routers, a system configuration as shown in Figure 1.0 may be realized.
Maximum flexibility is provided by allowing one board design to be
populated today using either IDT’s 75P42100 or 75P52100 IPCs and
later upgraded to use IDT’s 75K62100 IPC. Applications note AN-279
discusses how to accommodate one board design for any of these IPCs.
In this compatible configuration, the IPC interfaces directly to an
ASIC/ FPGA for lookups and routes an Index to an associated SRAM
device, which supplies the next hop address via an SRAM Data Bus to
the ASIC. The IPC provides the required control signals to directly
hookup to ZBT™ or Synchronous Pipeline Burst SRAM. Lookup results
can also be fed directly back to the ASIC/ FPGA without the use of external
SRAM. Control of the associated handshake signals is provided by all
IPCs to adapt to either configuration.
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Figure 1.0 ASIC / Compatible IPC / SRAM configuration
Network Interface
x
Full Ternary 32K x 72 bit content addressable memory
Upgradeable to 64K x 72 and 128K x 72 IPCs
Power Management
Global Mask Registers
Segments individually configurable
36/72/144/288/576 multiple width lookups
100M sustained lookups per second at 72 and 144 width lookups
Burst write for high speed table updates
Multi-match
Learn new entries
Dual bus interface
Cascadable to 8 devices with no glue logic or latency penalty
Glueless interface to standard ZBT™ or
Synchronous Pipelined Burst SRAMs
Boundary Scan JTAG Interface (IEEE 1149.1compliant)
1.8V core power supply
2.5V VBIAS power supply
User selectable 2.5V or 1.8V I/O supply
ASIC
or
FPGA
IDT
75P42100
or
75P52100
or
75K62100
IP Co-Processor
Optional
ZBT
or
Sync SRAM
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OCTOBER 2001
1
© 2002 Integrated Device Technology, Inc.
All rights reserved.
Product specifications subject to change without notice.
DSC-5346/01
