110 MSPS/140 MSPS
Analog Interface for Flat Panel Displays
AD9985A
FEATURES
AUTO-CLAMP
LEVEL ADJUST
RIN
RGB graphics processing
LCD monitors and projectors
Plasma display panels
Scan converters
Microdisplays
Digital TVs
8
ROUTA
AUTO-CLAMP
LEVEL ADJUST
GIN
A/D
CLAMP
8
GOUTA
AUTO-CLAMP
LEVEL ADJUST
BIN
A/D
CLAMP
8
COAST
FILT
DTACK
SYNC
PROCESSING
AND CLOCK
GENERATION
HSOUT
VSOUT
SOGOUT
SOGIN
REF
SCL
SDA
BOUTA
MIDSCV
HSYNC
CLAMP
APPLICATIONS
A/D
CLAMP
SERIAL REGISTER AND
POWER MANAGEMENT
A0
REF
BYPASS
AD9985A
05484-001
Variable analog input bandwidth control
Variable SOGIN bandwidth control
Automated clamping level adjustment
140 MSPS maximum conversion rate
300 MHz analog bandwidth
0.5 V to 1.0 V analog input range
500 ps p-p PLL clock jitter at 110 MSPS
3.3 V power supply
Full sync processing
Selectable input filtering
Sync detect for hot plugging
Midscale clamping
Power-down mode
Low power: 500 mW typical
4:2:2 output format mode
FUNCTIONAL BLOCK DIAGRAM
Figure 1.
GENERAL DESCRIPTION
The AD9985A is a complete 8-bit, 140 MSPS, monolithic
analog interface optimized for capturing RGB graphics signals
from personal computers and workstations. Its 140 MSPS
encode rate capability and full power analog bandwidth of 300
MHz support resolutions up to SXGA (1280 × 1024 at 75 Hz).
When the Coast signal is presented, the PLL maintains its
output frequency in the absence of Hsync. A sampling phase
adjustment is provided. Data, Hsync, and clock output phase
relationships are maintained. The AD9985A also offers full sync
processing for composite sync and sync-on-green applications.
The AD9985A includes a 140 MHz triple ADC with internal
1.25 V reference, a PLL, and programmable gain, offset, and
clamp control. The user provides only a 3.3 V power supply,
analog input, and horizontal sync (Hsync) and Coast signals.
Three-state CMOS outputs can be powered from 2.5 V to 3.3 V.
A clamp signal is generated internally or can be provided by the
user through the CLAMP input pin. This interface is fully
programmable via a 2-wire serial interface.
The AD9985A’s on-chip PLL generates a pixel clock from the
Hsync input. Pixel clock output frequencies range from 12 MHz
to 140 MHz. PLL clock jitter is 500 ps p-p typical at 140 MSPS.
Fabricated in an advanced CMOS process, the AD9985A is
provided in a space-saving 80-lead LQFP surface-mount
Pb-free plastic package, and is specified over the –40°C to
+85°C temperature range.
Rev. 0
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