200pin Unbuffered DDR2 SDRAM SO-DIMMs based on 1Gb version C
This Hynix unbuffered Small Outline Dual In-Line Memory Module(DIMM) series consists of 1Gb version C DDR2
SDRAMs in Fine Ball Grid Array(FBGA) packages on a 200pin glass-epoxy substrate. This Hynix 1Gb version C based
Unbuffered DDR2 SO-DIMM series provide a high performance 8 byte interface in 67.60mm width form factor of industry standard. It is suitable for easy interchange and addition.
FEATURES
•
JEDEC standard Double Data Rate 2 Synchronous
•
DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power
sequential and interleave mode
Supply
•
•
•
Posted CAS
•
Programmable CAS Latency 3 ,4 ,5, and 6
•
OCD (Off-Chip Driver Impedance Adjustment) and
ODT (On-Die Termination)
Fully differential clock operations (CK & CK)
Auto refresh and self refresh supported
•
8192 refresh cycles / 64ms
•
Serial presence detect with EEPROM
•
All inputs and outputs are compatible with SSTL_1.8
interface
•
Programmable Burst Length 4 / 8 with both
DDR2 SDRAM Package: 60 ball(x8) , 84 ball(x16)
FBGA
•
67.60 x 30.00 mm form factor
•
RoHS compliant
ORDERING INFORMATION
Density
Organization
# of
DRAMs
# of
ranks
Materials
HYMP164S64CP6-C4/Y5/S5/S6
512MB
64Mx64
4
1
Lead free
HYMP164S64CR6-C4/Y5/S5/S6
512MB
64Mx64
4
1
Halogen free
HYMP112S64CP6-C4/Y5/S5/S6
1GB
128Mx64
8
2
Lead free
HYMP112S64CR6-C4/Y5/S5/S6
1GB
128Mx64
8
2
Halogen free
HYMP125S64CP8-C4/Y5/S5/S6
2GB
256Mx64
16
2
Lead free
HYMP125S64CR8-C4/Y5/S5/S6
2GB
256Mx64
16
2
Halogen free
Part Name
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 1.0 / Dec. 2009
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