TC58FVM7 (T/B) 2AFT (65/80)
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
128-MBIT (16M × 8 BITS/8M × 16 BITS) CMOS FLASH MEMORY
DESCRIPTION
The TC58FVM7T2A/B2A is a 134217728-bit, 3.0-V read-only electrically erasable and programmable flash
memory organized as 16777216 × 8 bits or as 8388608 × 16 bits. The TC58FVM7T2A/B2A features commands for
Read, Program and Erase operations to allow easy interfacing with microprocessors. The commands are based on
the JEDEC standard. The Program and Erase operations are automatically executed in the chip. The
TC58FVM7T2A/B2A also features a Simultaneous Read/Write operation so that data can be read during a Write or
Erase operation.
FEATURES
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• Access Time (Random/Page)
Power supply voltage
VDD = 2.3 V~3.6 V
TC58FVM7T2A/B2AFT65 TC58FVM7T2A/B2AFT80
Operating temperature
VDD
CL = 30 pF CL = 100 pF CL = 30 pF CL = 100 pF
Ta = −40°C~85°C
Organization
2.7~3.6V 65 ns/25 ns 70 ns/30 ns 80 ns/30 ns 85 ns/35 ns
16M × 8 bits/8M × 16 bits
2.3~3.6V 70 ns/30 ns 75 ns/35 ns 85 ns/35 ns 90 ns/40 ns
Functions
• Power consumption
Simultaneous Read/Write
10 µA (Standby)
Page Read (8-word/16-byte)
15 mA (Program/Erase operation)
Auto Program, Auto Page Program
55 mA (Random Read operation)
Auto Block Erase, Auto Chip Erase
11 mA (Address Increment Read operation)
Fast Program Mode/Acceleration Mode
5 mA (Page Read operation)
Program Suspend/Resume
• Package
Erase Suspend/Resume
TSOPⅠ56-P-1420-0.50 (weight: 0.61g)
Data Polling/Toggle Bit
Block Protection, Boot Block Protection
Automatic Sleep, Support for Hidden ROM Area
Common Flash Memory Interface (CFI)
Byte/Word Modes
Block erase architecture
8 × 8 Kbytes/255 × 64 Kbytes
Boot block architecture
TC58FVM7T2A: top boot block
TC58FVM7B2A: bottom boot block
Mode control
Compatible with JEDEC standard commands
Erase/Program cycles
105 cycles typ.
2004-09-01
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