1 MSPS, 12-/10-/8-Bit ADCs
in 6-Lead SOT-23
AD7476/AD7477/AD7478
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Fast throughput rate: 1 MSPS
Specified for VDD of 2.35 V to 5.25 V
Low power
3.6 mW at 1 MSPS with 3 V supplies
15 mW at 1 MSPS with 5 V supplies
Wide input bandwidth
70 dB SNR at 100 kHz input frequency
Flexible power/serial clock speed management
No pipeline delays
High speed serial interface
SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible
Standby mode: 1 μA maximum
6-lead SOT-23 package
VDD
VIN
12-/10-/8-BIT
SUCCESSIVEAPPROXIMATION
ADC
SCLK
CONTROL
LOGIC
SDATA
CS
GND
01024-001
AD7476/AD7477/AD7478
Figure 1.
APPLICATIONS
Battery-powered systems
Personal digital assistants
Medical instruments
Mobile communications
Instrumentation and control systems
Data acquisition systems
High speed modems
Optical sensors
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The AD7476/AD7477/AD74781 are, respectively, 12-bit, 10-bit,
and 8-bit, high speed, low power, successive approximation
ADCs. The parts operate from a single 2.35 V to 5.25 V power
supply and feature throughput rates up to 1 MSPS. Each part
contains a low noise, wide bandwidth track-and-hold amplifier
that can handle input frequencies in excess of 6 MHz.
1.
First 12-/10-/8-Bit ADCs in SOT-23 Packages.
2.
High Throughput with Low Power Consumption.
3.
Flexible Power/Serial Clock Speed Management. The
conversion rate is determined by the serial clock, allowing
the conversion time to be reduced through the serial clock
speed increase. This allows the average power consumption
to be reduced while not converting. The parts also feature a
shutdown mode to maximize power efficiency at lower
throughput rates. Current consumption is 1 μA maximum
when in shutdown mode.
4.
Reference Derived from the Power Supply.
5.
No Pipeline Delay. The parts feature a standard successiveapproximation ADC with accurate control of the sampling
instant via a CS input and once-off conversion control.
The conversion process and data acquisition are controlled
using CS and the serial clock, allowing the devices to interface
with microprocessors or DSPs. The input signal is sampled on
the falling edge of CS and the conversion is initiated at this
point. There are no pipeline delays associated with these parts.
The AD7476/AD7477/AD7478 use advanced design techniques
to achieve very low power dissipation at high throughput rates.
The reference for the parts is taken internally from VDD. This
allows the widest dynamic input range to the ADC. Thus, the
analog input range for the parts are 0 V to VDD. The conversion
rate is determined by the SCLK.
1
Protected by U.S. Patent No. 6,681,332.
Rev. F
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