CY7C419/21/25/29/33256/512/1K/2K/4K x 9 Asynchronous FIFO CY7C419/21/25/29/33 256/512/1K/2K/4K x 9 Asynchronous FIFO Features • Asynchronous first-in first-out (FIFO) buffer memories • 256 x 9 (CY7C419) • 512 x 9 (CY7C421) • 1K x 9 (CY7C425) • 2K x 9 (CY7C429) • 4K x 9 (CY7C433) • Dual-ported RAM cell • High-speed 50.0-MHz read/write independent of depth/width • Low operating power: ICC = 35 mA • Empty and Full flags (Half Full flag in standalone) • TTL compatible • Retransmit in standalone • Expandable in width • PLCC, 7x7 TQFP, SOJ, 300-mil and 600-mil DIP • Pb-Free Packages Available • Pin compatible and functionally equivalent to IDT7200, IDT7201, IDT7202, IDT7203, IDT7204, AM7200, AM7201, AM7202, AM7203, and AM7204 Functional Description The CY7C419, CY7C420/1, CY7C424/5, CY7C428/9, and CY7C432/3 are first-in first-out (FIFO) memories offered in Cypress Semiconductor Corporation Document #: 38-06001 Rev. *B • 600-mil wide and 300-mil wide packages. They are, respectively, 256, 512, 1,024, 2,048, and 4,096 words by 9-bits wide. Each FIFO memory is organized such that the data is read in the same sequential order that it was written. Full and Empty flags are provided to prevent overrun and underrun. Three additional pins are also provided to facilitate unlimited expansion in width, depth, or both. The depth expansion technique steers the control signals from one device to another in parallel, thus eliminating the serial addition of propagation delays, so that throughput is not reduced. Data is steered in a similar manner. The read and write operations may be asynchronous; each can occur at a rate of 50.0 MHz. The write operation occurs when the write (W) signal is LOW. Read occurs when read (R) goes LOW. The nine data outputs go to the high-impedance state when R is HIGH. A Half Full (HF) output flag is provided that is valid in the standalone and width expansion configurations. In the depth expansion configuration, this pin provides the expansion out (XO) information that is used to tell the next FIFO that it will be activated. In the standalone and width expansion configurations, a LOW on the retransmit (RT) input causes the FIFOs to retransmit the data. Read enable (R) and write enable (W) must both be HIGH during retransmit, and then R is used to access the data. The CY7C419, CY7C420, CY7C421, CY7C424, CY7C425, CY7C428, CY7C429, CY7C432, and CY7C433 are fabricated using an advanced 0.65-micron P-well CMOS technology. Input ESD protection is greater than 2000V and latch-up is prevented by careful layout and guard rings. 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised June 30, 2005




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型式 数量 D/C・lead 備考 選択
CY7C433-10AC 8個 N/A N/A
CY7C433-10AC 10個    
CY7C433-10AC 2個    


型式 数量 D/C・lead 備考 選択
CY7C43310AC 10個    



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