MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MC74HC125A
MC74HC126A
Quad 3-State
Noninverting Buffers
High–Performance Silicon–Gate CMOS
The MC74HC125A and MC74HC126A are identical in pinout to the LS125
and LS126. The device inputs are compatible with standard CMOS outputs;
with pullup resistors, they are compatible with LSTTL outputs.
The HC125A and HC126A noninverting buffers are designed to be used
with 3–state memory address drivers, clock drivers, and other bus–oriented
systems. The devices have four separate output enables that are active–low
(HC125A) or active–high (HC126A).
• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 72 FETs or 18 Equivalent Gates
N SUFFIX
14–LEAD PLASTIC DIP PACKAGE
CASE 646–06
D SUFFIX
14–LEAD PLASTIC SOIC PACKAGE
CASE 751A–03
LOGIC DIAGRAM
HC125A
Active–Low Output Enables
A1
OE1
A2
OE2
2
3
HC126A
Active–High Output Enables
1
2
A1
Y1
6
4
MC74HCXXXAN
MC74HCXXXAD
MC74HCXXXADT
6
5
A2
Y2
ORDERING INFORMATION
Y1
1
OE1
5
3
DT SUFFIX
14–LEAD PLASTIC TSSOP PACKAGE
CASE 948G–01
Y2
PIN ASSIGNMENT
4
OE2
Plastic
SOIC
TSSOP
OE1
A3
9
8
Y3
8
9
A3
14
VCC
A1
Y3
1
2
13
OE4
Y1
OE3
A4
OE4
10
12
11
13
PIN 14 = VCC
PIN 7 = GND
FUNCTION TABLE
HC125A
Inputs
Output
HC126A
Inputs
Output
A
OE
Y
A
OE
Y
H
L
X
L
L
H
H
L
Z
H
L
X
H
H
L
H
L
Z
4/97
© Motorola, Inc. 1997
1
REV 8
Y4
5
10
OE3
Y2
13
OE4
A4
11
A2
Y4
12
4
6
9
A3
GND
11
12
A4
Y4
3
OE2
10
OE3
7
8
Y3