MOTOROLA Order this document by MTB75N05HD/D SEMICONDUCTOR TECHNICAL DATA HDTMOS E-FET.™ High Energy Power FET D2PAK for Surface Mount MTB75N05HD Motorola Preferred Device TMOS POWER FET 75 AMPERES 50 VOLTS RDS(on) = 9.5 mΩ N–Channel Enhancement–Mode Silicon Gate The D2PAK package has the capability of housing a larger die than any existing surface mount package which allows it to be used in applications that require the use of surface mount components with higher power and lower RDS(on) capabilities. This advanced high–cell density HDTMOS power FET is designed to withstand high energy in the avalanche and commutation modes. This new energy efficient design also offers a drain–to–source diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. • Avalanche Energy Specified • Source–to–Drain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode • Diode is Characterized for Use in Bridge Circuits • IDSS and VDS(on) Specified at Elevated Temperature • Short Heatsink Tab Manufactured — Not Sheared • Specially Designed Leadframe for Maximum Power Dissipation • Available in 24 mm 13–inch/800 Unit Tape & Reel, Add T4 Suffix to Part Number ™ D G CASE 418B–03, Style 2 D2PAK S MAXIMUM RATINGS (TC = 25°C unless otherwise noted) Symbol Value Unit Drain–to–Source Voltage VDSS 50 Volts Drain–to–Gate Voltage (RGS = 1.0 MΩ) VDGR 50 Gate–to–Source Voltage — Continuous VGS ± 20 Drain Current — Continuous Drain Current — Continuous @ 100°C Drain Current — Single Pulse (tp ≤ 10 µs) ID ID IDM 75 65 225 Amps Total Power Dissipation Derate above 25°C Total Power Dissipation @ TA = 25°C (minimum footprint, FR–4 board) PD 125 1.0 2.5 Watts W/°C Watts Rating TJ, Tstg – 55 to 150 °C Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C (VDD = 25 V, VGS = 10 V, Peak IL = 75 A, L = 0.177 mH, RG = 25 Ω) EAS 500 mJ Thermal Resistance — Junction to Case Thermal Resistance — Junction to Ambient Thermal Resistance — Junction to Ambient (minimum footprint, FR–4 board) RθJC RθJA RθJA 1.0 62.5 50 °C/W Maximum Temperature for Soldering Purposes, 1/8″ from case for 10 seconds TL 260 °C Operating and Storage Temperature Range This data sheet permits the design of most circuits entirely from the information presented. SOA Limit curves — representing boundaries on device characteristics — are given to facilitate “worst case” design. E–FET and HDTMOS are trademarks of Motorola Inc. TMOS is a registered trademark of Motorola, Inc. Thermal Clad is a trademark of the Bergquist Company. Preferred devices are Motorola recommended choices for future use and best overall value. REV 3 ©Motorola TMOS Power MOSFET Transistor Device Data Motorola, Inc. 1999 1






ON Semiconductor






Not pic File

「見積依頼」をクリックして どうぞお問合せ下さい。



5N05HDの取扱い販売会社 株式会社クレバーテック  会社情報(PDF)    戻る