Features • Eight General-purpose Floating-point Data Registers, Each Supporting a Full 80-bit • • • • • • • • • • • • • • • • Extended Precision Real Data Format (a 64-bit Mantissa Plus a Sign Bit, and a 15-bit Signed Exponent) A 67-bit Arithmetic Unit to Allow Very Fast Calculations with Intermediate are Precision Greater than the Extended Precision Format A 67-bit Barrel Shifter for High-speed Shifting Operations (for Normalizing etc.) Special-purpose Hardware for High-speed Conversion Between Single, Double, and Extended Formats and the Internal Extended Format An Independent State Machine to Control Main Processor Communication for Pipelined Instruction Processing Forty-six Instructions, Including 35 Arithmetic Operations Full Conformation to the IEEE 754 Standard, Including All Requirements and Suggestions Support of Functions Not Defined by the IEEE Standard, Including a Full Set of Trigonometric and Transcendental Functions Seven Data Type Types: Byte, Word and Long Integers; Single, Double, and Extended Precision Real Numbers; and Packed Binary Coded Decimal String Real Numbers Twenty-two Constants Available In The On-chip ROM, Including π, e, and Powers of 10 Virtual Memory/Machine Operations Efficient Mechanisms for Procedure Calls, Context Switches, and Interrupt Handling Fully Concurrent Instruction Execution with the Main Processor Fully Concurrent Instruction Execution of Multiple Floating-point Instructions Use with any Host Processor, on an 8-, 16- or 32-bit Data Bus Available in 16.67, 20, 25 and 33 MHz for Tc from -55°C to +125°C VCC = 5V ± 10% CMOS Enhanced Floating-point Co-processor TS68882 Description The TS68882 enhanced floating-point co-processor is a full implementation of the IEEE Standard for Binary Floating-Point Arithmetic (754) for use with the THOMSON TS68000 Family of microprocessors. It is a pin and software compatible upgrade of the TS68881 with optimized MPU interface that provides over 1.5 times the performance of the TS68881. It is implemented using VLSI technology to give systems designers the highest possible functionality in a physically small device. Intended primarily for use as a co-processor to the TS68020/68030 32-bit microprocessor units (MPUs), the TS68882 provides a logical extension to the main MPU integer data processing capabilities. It does this by providing a very high performance floating-point arithmetic unit and a set of floating-point data registers that are utilized in a manner that is analogous to the use of the integer data registers. The TS68882 instruction set is a natural extension of all earlier members of the TS68000 Family, and supports all of the addressing modes of the host MPU. Due to the flexible bus interface of the TS68000 Family, the TS68882 can be used with any of the MPU devices of the TS68000 Family, and it may also be used as a peripheral to non-TS68000 processors. Screening/Quality This product could be manufactured in full compliance with either: • DESC 5962-89436 • or According to ATMELGrenoble Standards F suffix CQFP 68 Ceramic Quad Flat Pack MIL-STD-883 Class B • R suffix PGA 68 Ceramic Pin Grid Array Rev. 2119A–HIREL–04/02 1 TS68882 Figure 1. TS68882 Simplified Block 3 2119A–HIREL–04/02



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