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709279

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HIGH-SPEED 32/16K x 16 SYNCHRONOUS DUAL-PORT STATIC RAM IDT709279/69S/L Features ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed clock to data access – Commercial: 6.5/7.5/9/12/15ns (max.) – Industrial: 12ns (max.) Low-power operation – IDT709279/69S Active: 950mW (typ.) Standby: 5mW (typ.) – IDT709279/69L Active: 950mW (typ.) Standby: 1mW (typ.) Flow-Through or Pipelined output mode on either port via the FT/PIPE pin Counter enable and reset features ◆ ◆ ◆ ◆ ◆ Dual chip enables allow for depth expansion without additional logic Full synchronous operation on both ports – 4ns setup to clock and 1ns hold on all control, data, and address inputs – Data input, address, and control registers – Fast 6.5ns clock to data out in the Pipelined output mode – Self-timed write allows fast cycle time – 10ns cycle time, 100MHz operation in Pipelined output mode Separate upper-byte and lower-byte controls for multiplexed bus and bus matching compatibility TTL- compatible, single 5V (±10%) power supply Industrial temperature range (–40°C to +85°C) is available for selected speeds Available in a 100-pin Thin Quad Flatpack (TQFP) package Functional Block Diagram R/WR UBR R/WL UBL CE0L CE1L 1 0 0/1 CE0R CE1R 1 0 0/1 LBR OER LBL OEL FT/PIPEL 0/1 1b 0b b a 1a 0a I/O8LI/O15L 0a 1a a b 0b 1b 0/1 FT/PIPER I/O8R-I/O15R I/O Control , , I/O Control I/O0L-I/O7L I/O0R-I/O7R A14R(1) A14L(1) A0L CLKL ADSL CNTENL CNTRSTL Counter/ Address Reg. MEMORY ARRAY Counter/ Address Reg. A0R CLKR ADSR CNTENR CNTRSTR 3243 drw 01 NOTE: 1. A14 X is a NC for IDT709269. JANUARY 2009 1 ©2009 Integrated Device Technology, Inc. DSC-3243/14 IDT709279/69S/L High-Speed 32/16K x 16 Synchronous Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges Pin Names Left Port Right Port Names CE0L, CE1L CE0R, CE1R Chip Enables (3) R/WL R/WR Read/Write Enable OEL OER Output Enable A0L - A14L(1) A0R - A14R(1) Address I/O0L - I/O15L I/O0R - I/O15R Data Input/Output CLKL CLKR Clock UBL UBR Upper Byte Select(2) LBL LBR Lower Byte Select(2) ADSL ADSR Address Strobe CNTENL CNTENR Counter Enable CNTRSTL CNTRSTR Counter Reset FT/PIPEL FT/PIPER Flow-Through/Pipeline VSS Power GND NOTES: 1. A14x is a NC for IDT709269. 2. LB and UB are single buffered regardless of state of FT/PIPE. 3. CEo and CE1 are single buffered when FT/PIPE = VIL, CEo and CE 1 are double buffered when FT/PIPE = VIH, i.e. the signals take two cycles to deselect. Ground 3243 tbl 01 Truth Table I—Read/Write and Enable Control(1,2,3) OE CLK CE0 CE1 UB LB R/W Upper Byte I/O8-15 Lower Byte I/O0-7 X ↑ H X X X X High-Z High-Z Deselected—Power Down X ↑ X L X X X High-Z High-Z Deselected—Power Down X ↑ L H H H X High-Z High-Z Both Bytes Deselected X ↑ L H L H L DIN High-Z Write to Upper Byte Only X ↑ L H H L L High-Z DIN Write to Lower Byte Only X ↑ L H L L L DIN DIN Write to Both Bytes L ↑ L H L H H DOUT High-Z Read Upper Byte Only L ↑ L H H L H High-Z DOUT Read Lower Byte Only L ↑ L H L L H DOUT DOUT Read Both Bytes H X L H L L X High-Z High-Z Outputs Disabled Mode 3243 tbl 02 NOTES: 1. "H" = VIH, "L" = VIL, "X" = Don't Care. 2. ADS, CNTEN, CNTRST = X. 3. OE is an asynchronous input signal. 6.42 3

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