128K X 36, 3.3V Synchronous IDT71V547S/XS SRAM with ZBT™ Feature, Burst Counter and Flow-Through Outputs Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ 128K x 36 memory configuration, flow-through outputs Supports high performance system speed - 95 MHz (8ns Clock-to-Data Access) ZBTTM Feature - No dead cycles between write and read cycles Internally synchronized signal eliminates the need to control OE Single R/W (READ/WRITE) control pin 4-word burst capability (Interleaved or linear) Individual byte write (BW1 - BW4) control (May tie active) Three chip enables for simple depth expansion Single 3.3V power supply (±5%) Packaged in a JEDEC standard 100-pin TQFP package The IDT71V547 contains address, data-in and control signal registers. The outputs are flow-through (no output data register). Output enable is the only asynchronous signal and can be used to disable the outputs at any given time. A Clock Enable (CEN) pin allows operation of the IDT71V547 to be suspended as long as necessary. All synchronous inputs are ignored when CEN is high and the internal device registers will hold their previous values. There are three chip enable pins (CE1, CE2, CE2) that allow the user to deselect the device when desired. If any one of these three is not active when ADV/LD is low, no new memory operation can be initiated and any burst in progress is stopped. However, any pending data transfers (reads or writes) will be completed. The data bus will tri-state one cycle after the chip was deselected or write initiated. The IDT71V547 has an on-chip burst counter. In the burst mode, the IDT71V547 can provide four cycles of data for a single address presented to the SRAM. The order of the burst sequence is defined by the LBO input pin. The LBO pin selects between linear and interleaved burst sequence. The ADV/LD signal is used to load a new external address (ADV/LD = LOW) or increment the internal burst counter (ADV/LD = HIGH). The IDT71V547 SRAM utilizes IDT's high-performance, high-volume 3.3V CMOS process, and is packaged in a JEDEC Standard 14mm x 20mm 100-pin thin plastic quad flatpack (TQFP) for high board density. Description The IDT71V547 is a 3.3V high-speed 4,718,592-bit (4.5 Megabit) synchronous SRAM organized as 128K x 36 bits. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus it has been given the name ZBTTM, or Zero Bus Turn-around. Address and control signals are applied to the SRAM during one clock cycle, and on the next clock cycle, its associated data cycle occurs, be it read or write. Pin Description Summary A0 - A16 Address Inputs Input Synchronous Three Chip Enables Input Synchronous OE Output Enable Input Asynchronous R/W Read/Write Signal Input Synchronous CEN Clock Enable Input Synchronous Individual Byte Write Selects Input Synchronous Clock Input N/A Advance Burst Address / Load New Address Input Synchronous Linear / Interleaved Burst Order Input Static I/O Synchronous 3.3V Power Supply Static Ground Supply Static CE1, CE2, CE2 BW1, BW2, BW3, BW4 CLK ADV/LD LBO I/O0 - I/O31, I/OP1 I/OP4 VDD VSS Data Input/Output 3822 tbl 01 ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc. OCTOBER 2008 1 ©2007 Integrated Device Technology, Inc. DSC-3822/04 IDT71V547, 128K x 36, 3.3V Synchronous SRAM with ZBT™ Feature, Burst Counter and Flow-Through Outputs ™ Commercial and Industrial Temperature Ranges Functional Block Diagram LBO 128K x 36 BIT MEMORY ARRAY Address A [0:16] D Q Address D Q Control CE1, CE2 CE2 R/W Input Register CEN ADV/LD BWx D DI DO Control Logic Q Clk Mux Clock Sel Gate OE , Data I/O [0:31], I/O P[1:4] 3822 drw 01 Recommended DC Operating Conditions Recommended Operating Temperature and Supply Voltage Grade Temperature VSS VDD Symbol Commercial 0OC to +70OC 0V 3.3V±5% VDD Supply Voltage Industrial -40OC to +85OC 0V 3.3V±5% VSS Ground VIH VIH 3822 tbl 03 VIL Parameter Min. Typ. Max. Unit 3.135 3.3 3.465 V 0 0 0 V Input High Voltage - Inputs 2.0 ____ 4.6 Input High Voltage - I/O 2.0 ____ Input Low Voltage (1) -0.5 ____ V (2) VDD+0.3 V 0.8 V 3822 tbl 04 NOTES: 1. VIL (min.) = –1.0V for pulse width less than tCYC/2, once per cycle. 2. VIH (max.) = +6.0V for pulse width less than tCYC/2, once per cycle. 3 6.42




Integrated Device Technology, Inc.




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