CMOS SyncFIFO™
512 x 36
1,024 x 36
2,048 x 36
FEATURES:
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Storage capacity:
IDT723631 - 512 x 36
IDT723641 - 1,024 x 36
IDT723651 - 2,048 x 36
Supports clock frequencies up to 67 MHz
Fast access times of 11ns
Free-running CLKA and CLKB can be asynchronous or coincident (permits simultaneous reading and writing of data on a
single clock edge)
Clocked FIFO buffering data from Port A to Port B
Synchronous read retransmit capability
Mailbox register in each direction
Programmable Almost-Full and Almost-Empty flags
Microprocessor interface control logic
Input Ready (IR) and Almost-Full (AF) flags synchronized by
CLKA
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IDT723631
IDT723641
IDT723651
Output Ready (OR) and Almost-Empty (AE) flags synchronized
by CLKB
Available in 132-pin plastic quad flat package (PQFP) or spacesaving 120-pin thin quad flat package (TQFP)
Industrial temperature range (–40°C to +85°C) is available
Green parts available, see ordering information
DESCRIPTION:
The IDT723631/723641/723651 is a monolithic high-speed, low-power,
CMOS clocked FIFO memory. It supports clock frequencies up to 67 MHz
and has read access times as fast as 12ns. The 512/1,024/2,048 x 36
dual-port SRAM FIFO buffers data from port A to Port B. The FIFO memory
has retransmit capability, which allows previously read data to be accessed again. The FIFO has flags to indicate empty and full conditions and
two programmable flags (Almost-Full and Almost-Empty) to indicate when a
selected number of words is stored in memory. Communication between
each port may take place with two 36-bit mailbox registers. Each mailbox
FUNCTIONAL BLOCK DIAGRAM
MBF1
RAM ARRAY
512 x 36
1,024 x 36
2,048 x 36
Reset
Logic
36
Write
Pointer
A0 - A35
Read
Pointer
IR
AF
Status Flag
Logic
FS0/SD
FS1/SEN
Sync
Retransmit
Logic
RST
Input
Register
Port-A
Control
Logic
Output
Register
Mail 1
Register
CLKA
CSA
W/RA
ENA
MBA
RTM
RFM
B0 - B35
Flag Offset
Registers
10
Mail 2
Register
OR
AE
Port-B
Control
Logic
CLKB
CSB
W/RB
ENB
MBB
3023 drw01
MBF2
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
FEBRUARY 2009
1
©2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-2023/7
IDT723631/723641/723651 CMOS SyncFIFO™
512 x 36, 1,024 x 36 and 2,048 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
GND
CLKA
ENA
W/RA
CSA
IR
OR
VCC
AF
AE
VCC
MBF2
MBA
RST
GND
FS0/SD
FS1/SEN
RTM
RFM
VCC
NC
MBB
GND
MBF1
GND
CSB
W/RB
ENB
CLKB
VCC
PIN CONFIGURATION (CONTINUED)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
B35
B34
B33
B32
GND
B31
B30
B29
B28
B27
B26
VCC
B25
B24
GND
B23
B22
B21
B20
B19
B18
GND
B17
B16
VCC
B15
B14
B13
B12
GND
GND
A11
A10
A9
A8
A7
A6
GND
A5
A4
A3
VCC
A2
A1
A0
GND
B0
B1
B2
B3
B4
B5
GND
B6
VCC
B7
B8
B9
B10
B11
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
A35
A34
A33
A32
VCC
A31
A30
GND
A29
A28
A27
A26
A25
A24
A23
GND
A22
VCC
A21
A20
A19
A18
GND
A17
A16
A15
A14
A13
VCC
A12
3023 drw03
TQFP (PN120-1, ORDER CODE: PF)
TOP VIEW
NOTE:
1. NC – No Connection
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