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74ABT16501
74ABT16501 18-Bit Universal Bus Transceivers with TRI-STATE Outputs General Description These 18-bit universal bus transceivers combine D-type latches and D-type flip-flops to allow data flow in transparent latched and clocked modes Data flow in each direction is controlled by output-enable (OEAB and OEBA) latch-enable (LEAB and LEBA) and clock (CLKAB and CLKBA) inputs For A-to-B data flow the device operates in the transparent mode when LEAB is high When LEAB is low the A data is latched if CLKAB is held at a high or low logic level If LEAB is low the A bus data is stored in the latch flip-flop on the low-to-high transition of CLKAB Output-enable OEAB is active-high When OEAB is high the outputs are active When OEAB is low the outputs are in the high-impedance state Data flow for B to A is similar to that of A to B but uses OEBA LEBA and CLKBA The output enables are complementary (OEAB is active high and OEBA is active low) To ensure the high-impedance state during power up or power down OE inputs should be tied to GND through a pulldown resistor the minimum value of the resistor is determined by the current-sourcing capability of the driver Features Y Y Y Y Y Combines D-Type latches and D-Type flip-flops for operation in transparent latched or clocked mode Flow-through architecture optimizes PCB layout Guaranteed latch-up protection High impedance glitch free bus loading during entire power up and power down cycle Non-destructive hot insertion capability Package Number Package Description 74ABT16501CSSC (Note 1) MS56A 56-Lead (0 300 Wide) Molded Shrink Small Outline JEDEC (SSOP) 74ABT16501CMTD (Notes 1 2) MTD56 56-Lead Molded Thin Shrink Small Outline JEDEC (TSSOP) Commercial Note 1 Devices also available in 13 reel Use suffix e SSCX and MTDX Note 2 Contact factory for package availability Connection Diagram Function Table Pin Assignment for SSOP Inputs OEAB LEAB CLKAB A Output B L H H H H H H X H H L L L L X X X X L H L H X X Z L H L H B0 B0 u u H L A-to-B data flow is shown B-to-A flow is similar but uses OEBA LEBA and CLKBA Output level before the indicated steady-state input conditions were established Output level before the indicated steady-state input conditions were established provided that CLKAB was high before LEAB went low TL F 11690 – 1 TRI-STATE is a registered trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation TL F 11690 RRD-B30M105 Printed in U S A 74ABT16501 18-Bit Universal Bus Transceivers with TRI-STATE Outputs September 1995 Absolute Maximum Ratings (Note 1) b 65 C to a 150 C VCC Pin Potential to Ground Pin b 500 mA Over Voltage Latchup (I O) 10V b 55 C to a 150 C Junction Temperature under Bias Plastic DC Latchup Source Current b 55 C to a 125 C Storage Temperature Ambient Temperature under Bias Note 1 Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired Functional operation under these conditions is not implied Note 2 Either voltage limit or current limit is sufficient to protect inputs b 0 5V to a 7 0V Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Any Output in the Disabled or Power-off State in the HIGH State b 0 5V to a 7 0V Recommended Operating Conditions b 30 mA to a 5 0 mA Free Air Ambient Temperature Commercial Current Applied to Output in LOW State (Max) twice the rated IOL (mA) b 40 C to a 85 C Supply Voltage Commercial b 0 5V to 5 5V b 0 5V to VCC a 4 5V to a 5 5V Minimum Input Edge Rate Data Input Enable Input (DV Dt) 50 mV ns 20 mV ns DC Electrical Characteristics Symbol ABT16501 Parameter VIH Input HIGH Voltage VIL Input Clamp Diode Voltage VOH Output HIGH Voltage Typ Input LOW Voltage VCD Min Max 20 Units VCC Conditions V Recognized HIGH Signal 08 V Recognized LOW Signal b1 2 V Min IIN e b18 mA 74ABT 25 V Min 74ABT 20 V Min IOH e b3 mA IOH e b32 mA 0 55 V Min 5 5 mA Max 7 mA Max b5 b5 mA Max V 00 50 mA 0 b 5 5V VOUT e 2 7V OE OE e 2 0V b 50 mA 0 b 5 5V VOUT e 0 5V OE OE e 2 0V VOL Output LOW Voltage IIH Input HIGH Current 74ABT IBVI Input HIGH Current Breakdown Test IIL Input LOW Current VID Input Leakage Test IIH a IOZH Output Leakage Current IIL a IOZL Output Leakage Current IOS Output Short-Circuit Current b 275 mA Max ICEX Output High Leakage Current 50 mA Max IZZ Bus Drainage Test 100 mA 00 ICCH Power Supply Current 10 mA Max All Outputs HIGH ICCL Power Supply Current 68 mA Max An or Bn Outputs Low ICCZ Power Supply Current 10 mA Max OEn e VCC All Others at VCC or GND ICCT Additional ICC Input 25 mA Max VI e VCC b 2 1V All Others at VCC or GND ICCD Dynamic ICC (Note 1) 0 23 mA MHz Max Outputs Open Transparent Mode One Bit Toggling 50% Duty Cycle 4 75 b 100 No Load Note 1 Guaranteed but not tested 3 IOL e 64 mA VIN e 2 7V (Note 1) VIN e VCC VIN e 7 0V VIN e 0 5V (Note 1) VIN e 0 0V IID e 1 9 mA All Other Pins Grounded VOUT e 0V VOUT e VCC VOUT e 5 5V All Others GND
TI
Texas Instruments Incorporated
U.S.A
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