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74ABT623D
74ABT623 Octal transceiver with dual enable; non-inverting; 3-state Rev. 03 — 22 October 2009 Product data sheet 1. General description The 74ABT623 high performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. The 74ABT623 is an octal transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. This octal bus transceiver is designed for asynchronous two-way communication between data buses. The control function implementation allows maximum flexibility in timing. This device allows data transmission from the A bus to the B bus or from the B bus to the A bus, depending upon the logic levels at the enable inputs (pins OEAB and OEBA). The enable inputs can be used to disable the device so that the buses are effectively isolated. The dual enable function configuration gives this transceiver the capability to store data by simultaneous enabling of pins OEAB and OEBA. Each output reinforces its input in this transceiver configuration. Thus, when both control inputs are enabled and all other data sources to the two sets of the bus lines are at high-impedance OFF-state, both sets of the bus lines will remain at their last states. The 8-bit codes appearing on the two sets of buses will be identical. 2. Features I I I I I I I Octal bidirectional bus interface 3-state buffers Power-up 3-state Output capability: +64 mA and −32 mA data inputs are disabled during 3-state mode Latch-up protection exceeds 500 mA per JESD78B class II level A ESD protection: N HBM JESD22-A114F exceeds 2000 V N MM JESD22-A115-A exceeds 200 V 74ABT623 NXP Semiconductors Octal transceiver with dual enable; non-inverting; 3-state 19 1 2 OEBA OEAB A0 B0 3 A1 B1 4 13 A6 B6 9 14 A5 B5 8 15 A4 B4 7 16 A3 B3 6 17 A2 B2 5 18 12 A7 B7 11 001aaa832 Fig 3. Logic diagram 74ABT623_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 22 October 2009 3 of 15
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