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74AC273D
54AC 74AC273 Octal D Flip-Flop General Description Features The ’273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs The common buffered Clock (CP) and Master Reset (MR) input load and reset (clear) all flip-flops simultaneously The register is fully edge-triggered The state of each D input one setup time before the LOW-to-HIGH clock transition is transferred to the corresponding flip-flop’s Q output All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR input The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements Y Y Y Y Y Y Y Y Y Y Ideal buffer for microprocessor or memory Eight edge-triggered D flip-flops Buffered common clock Buffered asynchronous master reset See ’377 for clock enable version See ’373 for transparent latch version See ’374 for TRI-STATE version Outputs source sink 24 mA ’ACT has TTL-compatible inputs Standard Military Drawing (SMD) ’AC273 5962-87756 Logic Symbols Connection Diagrams Pin Assignment for DIP Flatpak and SOIC IEEE IEC TL F 9954–1 TL F 9954 – 2 TL F 9954 – 3 Pin Assignment for LCC Pin Names D0 –D7 MR CP Q0 – Q7 Description Data Inputs Master Reset Clock Pulse Input Data Outputs FACTTM is a trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation TL F 9954 TL F 9954 – 4 RRD-B30M75 Printed in U S A 54AC 74AC273 Octal D Flip-Flop August 1993 Absolute Maximum Rating (Note 1) Recommended Operating Conditions If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage (VCC) DC Input Diode Current (IIK) VI e b0 5V VI e VCC a 0 5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO e b0 5V VO e VCC a 0 5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) Junction Temperature (TJ) CDIP PDIP Supply Voltage (VCC) ’AC Input Voltage (VI) b 0 5V to a 7 0V 2 0V to 6 0V 0V to VCC 0V to VCC Output Voltage (VO) Operating Temperature (TA) 74AC 54AC b 20 mA a 20 mA b 0 5V to VCC a 0 5V b 40 C to a 85 C b 55 C to a 125 C Minimum Input Edge Rate (DV Dt) ’AC Devices VIN from 30% to 70% of VCC VCC 3 3V 4 5V 5 5V b 20 mA a 20 mA b 0 5V to to VCC a 0 5V 125 mV ns g 50 mA g 50 mA b 65 C to a 150 C 175 C 140 C Note 1 Absolute maximum ratings are those values beyond which damage to the device may occur The databook specifications should be met without exception to ensure that the system design is reliable over its power supply temperature and output input loading variables National does not recommend operation of FACT TM circuits outside databook specifications DC Characteristics for ’AC Family Devices 74AC Symbol Parameter VCC (V) 54AC 74AC TA e a 25 C TA e b 55 C to a 125 C TA e b 40 C to a 85 C Typ VIH Units Conditions Guaranteed Limits VOH 30 45 55 15 2 25 2 75 21 3 15 3 85 21 3 15 3 85 21 3 15 3 85 V VOUT e 0 1V or VCC b 0 1V Maximum Low Level Input Voltage 30 45 55 15 2 25 2 75 09 1 35 1 65 09 1 35 1 65 09 1 35 1 65 V VOUT e 0 1V or VCC b 0 1V Minimum High Level Output Voltage 30 45 55 2 99 4 49 5 49 29 44 54 29 44 54 29 44 54 V 2 56 3 86 4 86 24 37 47 2 46 3 76 4 76 V 01 01 01 01 01 01 01 01 01 V 30 45 55 VIL Minimum High Level Input Voltage 0 36 0 36 0 36 0 50 0 50 0 50 0 44 0 44 0 44 V 55 g0 1 g1 0 g1 0 mA 30 45 55 VOL IIN Maximum Low Level Output Voltage Maximum Input Leakage Current 30 45 55 0 002 0 001 0 001 All outputs loaded thresholds on input associated with output under test Maximum test duration 2 0 ms one output loaded at a time 3 IOUT e b50 mA VIN e VIL or VIH b 12 mA b 24 mA IOH b 24 mA IOUT e 50 mA VIN e VIL or VIH 12 mA IOL 24 mA 24 mA VI e VCC GND
MOT
1999年8月4日、ディスクリート・標準アナログ・標準ロジックなどの半導体部門をオン・セミコンダクターとして分社化した。これは、イリジウムコミュニケーションズ倒産の損失をカバーするために分社化された。
ON Semiconductor
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