74ALVT16821
20-bit bus interface D-type flip-flop; positive-edge trigger;
3-state
Rev. 03 — 13 June 2005
Product data sheet
1. General description
The 74ALVT16821 high-performance Bipolar Complementary Metal Oxide
Semiconductor (BiCMOS) device combines low static and dynamic power dissipation with
high speed and high output drive. It is designed for VCC operation at 2.5 V or 3.3 V with
I/O compatibility to 5 V.
The 74ALVT16821 has two 10-bit, edge triggered registers, with each register coupled to
a 3-state output buffer. The two sections of each register are controlled independently by
the clock (nCP) and output enable (nOE) control gates.
Each register is fully edge triggered. The state of each D input, one set-up time before the
LOW-to-HIGH clock transition, is transferred to the corresponding flip-flops Q output.
The 3-state output buffers are designed to drive heavily loaded 3-state buses, MOS
memories, or MOS microprocessors.
The active low output enable (nOE) controls all ten 3-state buffers independent of the
register operation. When nOE is LOW, the data in the register appears at the outputs.
When nOE is HIGH, the outputs are in high-impedance OFF-state, which means they will
neither drive nor load the bus.
2. Features
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20-bit positive-edge triggered register
5 V I/O compatible
Multiple VCC and GND pins minimize switching noise
Bus hold data inputs eliminate the need for external pull-up resistors to hold unused
inputs
Live insertion and extraction permitted
Power-up reset
Power-up 3-state
Output capability: +64 mA and −32 mA
Latch-up protection:
x JESD78: exceeds 500 mA
ESD protection:
x MIL STD 883, method 3015: exceeds 2000 V
x Machine model: exceeds 200 V
