®
IDT54/74FCT373/A/C
IDT54/74FCT533/A/C
IDT54/74FCT573/A/C
FAST CMOS OCTAL
TRANSPARENT LATCHES
Integrated Device Technology, Inc.
FEATURES
DESCRIPTION
• IDT54/74FCT373/533/573 equivalent to FAST™ speed
and drive
• IDT54/74FCT373A/533A/573A up to 30% faster than
FAST
• Equivalent to FAST output drive over full temperature
and voltage supply extremes
• IOL = 48mA (commercial) and 32mA (military)
• CMOS power levels (1mW typ. static)
• Octal transparent latch with 3-state output control
• JEDEC standard pinout for DIP and LCC
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class B
The IDT54/74FCT373/A/C, IDT54/74FCT533/A/C and
IDT54/74FCT573/A/C are octal transparent latches built using an advanced dual metal CMOS technology. These octal
latches have 3-state outputs and are intended for bus oriented
applications. The flip-flops appear transparent to the data
when Latch Enable (LE) is HIGH. When LE is LOW, the data
that meets the set-up time is latched. Data appears on the bus
when the Output Enable (OE) is LOW. When OE is HIGH, the
bus output is in the high-impedance state.
FUNCTIONAL BLOCK DIAGRAMS
IDT54/74FCT373 AND IDT54/74FCT573
D0
D1
D
D2
D
D3
D
O
D
O
G
D4
D
O
G
D5
D
O
G
D6
D
O
G
D7
D
O
G
O
G
O
G
G
LE
OE
O0
O1
O2
O3
O4
O5
O6
O7
2602 cnv* 01
IDT54/74FCT533
D0
D1
D
D2
D
D3
D
O
D
O
G
D4
D
O
G
D5
D
O
G
D6
D
O
G
D7
D
O
G
O
G
O
G
G
LE
OE
O0
O1
O2
O3
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FAST is a trademark of National Semiconductor Co.
O5
O6
O7
2602 cnv* 02
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1992 Integrated Device Technology, Inc.
O4
7.12
MAY 1992
DSC-4624/2
1
IDT54/74FCT373/533/573/A/C
FAST CMOS OCTAL TRANSPARENT LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTION TABLE (FCT373 and FCT573)(1)
FUNCTION TABLE (FCT533)(1)
Inputs
LE
DN
Outputs
OE
ON
DN
Inputs
LE
OE
Outputs
ON
H
H
L
L
H
H
L
H
L
H
L
H
L
H
L
L
X
X
H
Z
X
X
H
Z
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High Impedance
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High Impedance
2602 tbl 05
2602 tbl 06
PIN DESCRIPTION
Pin Names
DN
Description
Data Inputs
LE
Latch Enable Input (Active HIGH)
OE
Output Enable Input (Active LOW)
ON
3-State Outputs
ON
Complementary 3-State Outputs
2602 tbl 07
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
Commercial
VTERM(2) Terminal Voltage
–0.5 to +7.0
with Respect to
GND
VTERM(3) Terminal Voltage
–0.5 to VCC
with Respect to
GND
TA
Operating
0 to +70
Temperature
TBIAS
Temperature
–55 to +125
Under Bias
TSTG
Storage
–55 to +125
Temperature
PT
Power Dissipation
0.5
IOUT
DC Output
Current
120
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Military
–0.5 to +7.0
Unit
V
–0.5 to VCC
V
–55 to +125
°C
–65 to +135
°C
–65 to +150
°C
0.5
W
120
mA
Symbol
Parameter
CIN
Input
Capacitance
COUT
Output
Capacitance
Conditions
VIN = 0V
Typ.
6
Max.
10
Unit
pF
VOUT = 0V
8
12
pF
NOTE:
2602 tbl 02
1. This parameter is measured at characterization but not tested.
NOTES:
2602 tbl 01
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed VCC by +0.5V unless otherwise noted.
2. Input and VCC terminals only.
3. Outputs and I/O terminals only.
7.12
3
