MC10131
Dual Type D Master-Slave
Flip-Flop
The MC10131 is a dual master–slave type D flip–flop.
Asynchronous Set (S) and Reset (R) override Clock (CC) and Clock
Enable (CE) inputs. Each flip–flop may be clocked separately by
holding the common clock in the low state and using the enable inputs
for the clocking function. If the common clock is to be used to clock
the flip–flop, the Clock Enable inputs must be in the low state. In this
case, the enable inputs perform the function of controlling the
common clock.
The output states of the flip–flop change on the positive transition of
the clock. A change in the information present at the data (D) input
will not affect the output information at any other time due to master
slave construction.
• PD = 235 mW typ/pkg (No Load)
• FTog = 160 MHz typ
• tpd = 3.0 ns typ
• tr, tf = 2.5 ns typ (20%–80%)
http://onsemi.com
MARKING
DIAGRAMS
16
CDIP–16
L SUFFIX
CASE 620
MC10131L
AWLYYWW
1
16
PDIP–16
P SUFFIX
CASE 648
MC10131P
AWLYYWW
1
1
DIP PIN ASSIGNMENT
VCC1
1
16
Q1
2
15
Q2
Q1
3
14
Q2
R1
4
13
R2
S1
5
12
S2
CE1
6
11
D1
10
D2
VEE
8
9
CC
10131
CE2
7
PLCC–20
FN SUFFIX
CASE 775
VCC2
A
WL
YY
WW
AWLYYWW
= Assembly Location
= Wafer Lot
= Year
= Work Week
CLOCKED TRUTH TABLE
C
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion Tables on page 18
of the ON Semiconductor MECL Data Book (DL122/D).
LOGIC DIAGRAM
D
Qn+1
L
X
Qn
H
L
L
H
H
H
C = CE + CC.A clock H is a clock transition from a low to a
high state.
S1 5
R–S TRUTH TABLE
D1 7
Q1
2
Q1
3
R
Qn+1
L
Qn
L
R1 4
CC 9
R2 13
S
L
CE1 6
H
H
H
L
L
H
H
N.D.
N.D. = Not Defined
Q2
Q2
CE2 11
D2 10
14
15
ORDERING INFORMATION
Device
© Semiconductor Components Industries, LLC, 2002
January, 2002 – Rev. 7
25 Units / Rail
PDIP–16
25 Units / Rail
MC10131FN
1
CDIP–16
MC10131P
VCC1 = PIN 1
VCC2 = PIN 16
VEE = PIN 8
Shipping
MC10131L
S2 12
Package
PLCC–20
46 Units / Rail
Publication Order Number:
MC10131/D
