TLC555
LinCMOS TIMER
SLFS043E – SEPTEMBER 1983 – REVISED MARCH 2001
D Very Low Power Consumption
D
D
D
D
D
GND
TRIG
OUT
RESET
8
2
7
3
6
4
5
VDD
DISCH
THRES
CONT
FK PACKAGE
(TOP VIEW)
NC
TRIG
NC
OUT
NC
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
NC
DISCH
NC
THRES
NC
PW PACKAGE
(TOP VIEW)
description
The TLC555 is a monolithic timing circuit
fabricated using the TI LinCMOS process. The
timer is fully compatible with CMOS, TTL, and
MOS logic and operates at frequencies up to
2 MHz. Because of its high input impedance, this
device uses smaller timing capacitors than those
used by the NE555. As a result, more accurate
time delays and oscillations are possible. Power
consumption is low across the full range of power
supply voltage.
1
CONT
NC
D
(TOP VIEW)
NC
GND
NC
VDD
NC
D
– 1 mW Typ at VDD = 5 V
Capable of Operation in Astable Mode
CMOS Output Capable of Swinging Rail
to Rail
High Output-Current Capability
– Sink 100 mA Typ
– Source 10 mA Typ
Output Fully Compatible With CMOS, TTL,
and MOS
Low Supply Current Reduces Spikes
During Output Transitions
Single-Supply Operation From 2 V to 15 V
Functionally Interchangeable With the
NE555; Has Same Pinout
ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015.2
Available in Q-Temp Automotive
High Reliability Automotive Applications
Configuration Control/Print Support
Qualification to Automotive Standards
NC
RESET
NC
D
D
D, DB, JG, OR P PACKAGE
GND
NC
TRIG
NC
OUT
NC
RESET
1
2
3
4
5
6
7
14
13
12
11
10
9
8
VDD
NC
DISCH
NC
THRES
NC
CONT
NC – No internal connection
Like the NE555, the TLC555 has a trigger level equal to approximately one-third of the supply voltage and a
threshold level equal to approximately two-thirds of the supply voltage. These levels can be altered by use of
the control voltage terminal (CONT). When the trigger input (TRIG) falls below the trigger level, the flip-flop is
set and the output goes high. If TRIG is above the trigger level and the threshold input (THRES) is above the
threshold level, the flip-flop is reset and the output is low. The reset input (RESET) can override all other inputs
and can be used to initiate a new timing cycle. If RESET is low, the flip-flop is reset and the output is low.
Whenever the output is low, a low-impedance path is provided between the discharge terminal (DISCH) and
GND. All unused inputs should be tied to an appropriate logic level to prevent false triggering.
While the CMOS output is capable of sinking over 100 mA and sourcing over 10 mA, the TLC555 exhibits greatly
reduced supply-current spikes during output transitions. This minimizes the need for the large decoupling
capacitors required by the NE555.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
LinCMOS is a trademark of Texas Instruments.
Copyright 2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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