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74LV595D-T
74LV595 8-bit serial-in/serial-out or parallel-out shift register; 3-state Rev. 03 — 21 April 2009 Product data sheet 1. General description The 74LV595 is an 8 stage serial shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. It is a low-voltage Si-gate CMOS device and is pin and functionally compatible with the 74HC595 and 74HCT595. Data is shifted on the positive-going transitions of the SHCP input. The data in the shift register is transferred to the storage register on a positive-going transition of the STCP input. If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register. The shift register has a serial input (DS) and a serial output (Q7S) for cascading the device. It is also provided with an asynchronous reset input MR (active LOW) for all 8 shift register stages. The storage register has 8 parallel 3-state bus driver outputs. Data in the storage register appears at the output whenever the output enable input (OE) is LOW. 2. Features I I I I I I I I I Optimized for low voltage applications: 1.0 V to 3.6 V Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V Typical output ground bounce < 0.8 V at VCC = 3.3 V and Tamb = 25 °C Typical HIGH-level output voltage (VOH) undershoot: > 2 V at VCC = 3.3 V and Tamb = 25 °C Specified from −40 °C to +85 °C and from −40 °C to +125 °C Has a shift register with direct clear Multiple package options Output capability: N Parallel outputs; bus driver N serial output; standard ESD protection: N HBM JESD22-A114E exceeds 2000 V N MM JESD22-A115-A exceeds 200 V 3. Applications I Serial-to-parallel data conversion I Remote control holding register
PHILIPS
2006年8月フィリップス社が半導体部門を投資家グループに売却しKASLION Acquisition B.V.の名称で法人化。2010年5月 社名を現在のNXPセミコンダクターズN.V.に変更。
NXP
NXP Semiconductors
オランダ
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