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部品型式

AD7591AS

製品説明
仕様・特性

Data Sheet October 1997 L7591 Subscriber Line Interface Circuit Protector Features Description s Shunts lightning pulses to ground — Positive or negative 30 A, 10 x 1000 µs — Positive or negative 40 A, 5 x 320 µs — Positive or negative 80 A, 2 x 10 µs s Power-cross protection — 3.5 APEAK, 50 Hz to 60 Hz, 1 s — 5.0 APEAK, 50 Hz to 60 Hz, 10 ms s Gate trigger current, 15 mA max s Up to –80 V capability s Holding current, 150 mA min The L7591 Subscriber Line Interface Circuit (SLIC) Protector is designed to protect line-feed circuitry from fault-induced lightning and power-cross surge pulses. If a fault current forces TIP and/or RING to a more negative voltage than VS, current is conducted through the trip circuit. When the specified trip current level is reached, transistors PNPN1 and/or PNPN2 will turn on and "crowbar" the majority of the current to ground. If similar pulses force TIP and/or RING to a more positive state than ground, diodes D1 and/or D2 will conduct the pulse to ground. The L7591 SLIC Protector is available in an 8-pin, plastic DIP (L7591AB) and in an 8-pin, plastic SONB package (L7591AS). Pin Information Table 1. Pin Description (Applies to DIP and SONB packages) Pin Symbol 1 2 TIP VS 3 4 5 — RING PR 6 GND 7 GND 8 PT TIP TRIP CIRCUIT Name/Function Tip signal from customer. Supply voltage to gate (–20 V to –80 V). Test Point, do not use. Ring signal from customer. Protected ring signal to line-feedcircuitry. Device ground/fault current return. Device ground/fault current return. Protected tip signal to line-feed circuitry. Note: Pins 1 and 4 must always be connected to the protection resistors shown in Figures 4 and 5 (Line Feed Circuitry). The SLIC can be connected either to the protected outputs (pins 5 and 8) or to the inputs (pins 1 and 4). 8 PT 1 D1 PNPN1 VS 2 TEST POINT 3 7 GND 6 GND PNPN2 TRIP CIRCUIT RING D2 5 PR 4 12-1590 (C) Figure 1. Functional and Pin Diagram

ブランド

AD

会社名

Analog Devices

本社国名

U.S.A

事業概要

半導体デバイスを製造するアメリカの多国籍企業。特にADC、DAC、MEMS、DSPなどに強い。現在は 65nm から 3μm のプロセスルールの回路を設計している。

供給状況

 
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