a
DSP Microcomputer
ADSP-21065L
SDRAM Controller for Glueless Interface to Low Cost
External Memory (@ 66 MHz)
64M Words External Address Range
12 Programmable I/O Pins and Two Timers with Event
Capture Options
Code-Compatible with ADSP-2106x Family
208-Lead MQFP or 196-Ball Mini-BGA Package
3.3 Volt Operation
SUMMARY
High Performance Signal Computer for Communications, Audio, Automotive, Instrumentation and
Industrial Applications
Super Harvard Architecture Computer (SHARC®)
Four Independent Buses for Dual Data, Instruction,
and I/O Fetch on a Single Cycle
32-Bit Fixed-Point Arithmetic; 32-Bit and 40-Bit FloatingPoint Arithmetic
544 Kbits On-Chip SRAM Memory and Integrated I/O
Peripheral
I2S Support, for Eight Simultaneous Receive and Transmit Channels
Flexible Data Formats and 40-Bit Extended Precision
32-Bit Single-Precision and 40-Bit Extended-Precision IEEE
Floating-Point Data Formats
32-Bit Fixed-Point Data Format, Integer and Fractional,
with Dual 80-Bit Accumulators
KEY FEATURES
66 MIPS, 198 MFLOPS Peak, 132 MFLOPS Sustained
Performance
User-Configurable 544 Kbits On-Chip SRAM Memory
Two External Port, DMA Channels and Eight Serial
Port, DMA Channels
Parallel Computations
Single-Cycle Multiply and ALU Operations in Parallel with
Dual Memory Read/Writes and Instruction Fetch
Multiply with Add and Subtract for Accelerated FFT Butterfly Computation
1024-Point Complex FFT Benchmark: 0.274 ms (18,221
Cycles)
32 ؋ 48 BIT
TWO INDEPENDENT
DUAL-PORTED BLOCKS
PROCESSOR PORT
ADDR
ADDR
DAG1
8 ؋ 4 ؋ 32
DAG2
DATA
DATA
I/O PORT
DATA
ADDR
ADDR
DATA
JTAG
BLOCK 1
INSTRUCTION
CACHE
BLOCK 0
DUAL-PORTED SRAM
CORE PROCESSOR
PROGRAM
SEQUENCER
8 ؋ 4 ؋ 24
24
32
IOD
48
DM ADDRESS BUS
48
IOA
17
PM ADDRESS BUS
7
TEST &
EMULATION
EXTERNAL
PORT
SDRAM
INTERFACE
PM DATA BUS
ADDR BUS
MUX
24
MULTIPROCESSOR
INTERFACE
BUS
CONNECT
(PX)
DATA BUS
MUX
40 DM DATA BUS
32
HOST PORT
DATA
REGISTER
FILE
MULTIPLIER
16 ؋ 40 BIT
IOP
REGISTERS
DMA
CONTROLLER
(2 Rx, 2Tx)
(MEMORY MAPPED)
BARREL
SHIFTER
ALU
CONTROL,
STATUS, TIMER
&
DATA BUFFERS
4
SPORT 0
(I2S)
(2 Rx, 2Tx)
SPORT 1
(I2S)
I/O PROCESSOR
Figure 1. Functional Block Diagram
SHARC is a registered trademark of Analog Devices, Inc.
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© 2003 Analog Devices, Inc. All rights reserved.
