SHARC Processor
ADSP-21161N
SUMMARY
Integrated peripherals—integrated I/O processor, 1M bit onchip dual-ported SRAM, SDRAM controller, glueless multiprocessing features, and I/O ports (serial, link, external
bus, SPI, and JTAG)
ADSP-21161N supports 32-bit fixed, 32-bit float, and 40-bit
floating-point formats
100 MHz/110 MHz core instruction rate
Single-cycle instruction execution, including SIMD operations in both computational units
Up to 660 MFLOPs peak and 440 MFLOPs sustained
performance
225-ball 17 mm 17 mm CSP_BGA package
High performance 32-Bit DSP—applications in audio, medical, military, wireless communications, graphics, imaging,
motor-control, and telephony
Super Harvard Architecture—four independent buses for
dual data fetch, instruction fetch, and nonintrusive zerooverhead I/O
Code compatible with all other sharc family DSPs
Single-instruction multiple-data (SIMD) computational architecture—two 32-bit IEEE floating-point computation units,
each with a multiplier, ALU, shifter, and register file
Serial ports offer I2S support via 8 programmable and simultaneous receive or transmit pins, which support up to 16
transmit or 16 receive channels of audio
DUAL-PORTED SRAM
INSTRUCTION
CACHE
32 48-BIT
DAG1
4 32
8
DAG2
4 32
DATA
DATA
ADDR
8
I/O PORT
PROCESSOR PORT
ADDR
BLOCK 0
TIMER
TWO INDEPENDENT
DUAL-PORTED BLOCKS
DATA
ADDR
DATA
JTAG TEST
AND EMULATION
BLOCK 1
CORE PROCESSOR
GPIO
FLAGS
SDRAM
CONTROLLER
IOD
64
PM ADDRESS BUS
12
ADDR
PROGRAM
SEQUENCER
32
6
IOA
18
8
EXTERNAL PORT
ADDR BUS
MUX
32
24
DM ADDRESS BUS
64
BUS
CONNECT
(PX)
PM DATA BUS
MULTIPROCESSOR
INTERFACE
64
DM DATA BUS
DATA BUS
MUX
MULT
DATA
REGISTER
FILE
(PEX)
16 40-BIT
BARREL
SHIFTER
ALU
BARREL
SHIFTER
DATA
REGISTER
FILE
(PEY)
16 40-BIT
32
HOST PORT
MULT
IOP
REGISTERS
(MEMORY MAPPED)
ALU
S
CONTROL,
STATUS, &
DATA BUFFERS
DMA
CONTROLLER
5
16
SERIAL PORTS (4)
20
LINK PORTS (2)
SPI PORTS (1)
4
I/O PROCESSOR
Figure 1. ADSP-21161N Functional Block Diagram
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
Rev. C
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