049BV33
CY7C1049BV33
512K x 8 Static RAM
Features
• High speed
— tAA = 15 ns
• Low active power
— 504 mW (max.)
• Low CMOS standby power (Commercial L version)
— 1.8 mW (max.)
• 2.0V Data Retention (660 µW at 2.0V retention)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features
Functional Description[1]
The CY7C1049BV33 is a high-performance CMOS Static
RAM organized as 524,288 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE), an
active LOW Output Enable (OE), and three-state drivers. Writing to the device is accomplished by taking Chip Enable (CE)
and Write Enable (WE) inputs LOW. Data on the eight I/O pins
(I/O0 through I/O7) is then written into the location specified on
the address pins (A0 through A18).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
The CY7C1049BV33 is available in a standard 400-mil-wide
36-pin SOJ and 44-pin TSOPII packages with center power
and ground (revolutionary) pinout.
Logic Block Diagram
Pin Configuration
SOJ
Top View
A0
A1
A2
A3
A4
CE
I/O0
I/O1
VCC
GND
I/O2
I/O3
WE
A5
A6
A7
A8
A9
I/O0
INPUT BUFFER
CE
I/O1
I/O2
512K x 8
ARRAY
SENSE AMPS
ROW DECODER
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
I/O3
I/O4
I/O5
COLUMN
DECODER
I/O6
POWER
DOWN
I/O7
OE
A 11
A 12
A 13
A14
A15
A16
A17
A18
WE
TSOP II
Top View
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
NC
A18
A17
A16
A15
OE
I/O7
I/O6
GND
VCC
I/O5
I/O4
A14
A13
A12
A11
A10
NC
NC
NC
A0
A1
A2
A3
A4
CE
I/O0
I/O1
VCC
VSS
I/O2
I/O3
WE
A5
A6
A7
A8
A9
NC
NC
1
44
2
3
43
42
4
5
6
41
40
39
7
38
8
9
36
10
11
12
37
35
34
33
13
32
14
15
16
17
18
19
20
21
22
31
30
29
28
27
26
25
24
23
NC
NC
NC
A18
A17
A16
A15
OE
I/O7
I/O6
VSS
VCC
I/O5
I/O4
A14
A13
A12
A11
A10
NC
NC
NC
Selection Guide
-12
-15
-17
-20
-25
Maximum Access Time (ns)
12
15
17
20
25
Maximum Operating Current (mA) Comm’l
200
180
170
160
150
220
200
180
170
170
8
8
8
8
8
0.5
0.5
0.5
0.5
0.5
Ind’l
Maximum CMOS Standby
Current (mA)
Com’l/Ind’l
Com’l
L
Note:
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05139 Rev. *A
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised September 13, 2002
