50
CY7C150
1Kx4 Static RAM
Features
Separate I/O paths eliminates the need to multiplex data in
and data out, providing for simpler board layout and faster system performance. Outputs are three-stated during write, reset,
deselect, or when output enable (OE) is held HIGH, allowing
for easy memory expansion.
• Memory reset function
• 1024 x 4 static RAM for control store in high-speed computers
• CMOS for optimum speed/power
• High speed
— 10 ns (commercial)
Reset is initiated by selecting the device (CS = LOW) and taking the reset (RS) input LOW. Within two memory cycles all
bits are internally cleared to zero. Since chip select must be
LOW for the device to be reset, a global reset signal can be
employed, with only selected devices being cleared at any given time.
— 12 ns (military)
• Low power
— 495 mW (commercial)
•
•
•
•
Writing to the device is accomplished when the chip select
(CS) and write enable (WE) inputs are both LOW. Data on the
four data inputs (D0−D3) is written into the memory location
specified on the address pins (A0 through A9).
— 550 mW (military)
Separate inputs and outputs
5-volt power supply ±10% tolerance in both commercial
and military
Capable of withstanding greater than 2001V static discharge
TTL-compatible inputs and outputs
Reading the device is accomplished by taking chip select (CS)
and output enable (OE) LOW while write enable (WE) remains
HIGH. Under these conditions, the contents of the memory
location specified on the address pins will appear on the four
output pins (O0 through O3).
Functional Description
The output pins remain in high-impedance state when chip
enable (CE) or output enable (OE) is HIGH, or write enable
(WE) or reset (RS) is LOW.
The CY7C150 is a high-performance CMOS static RAM designed for use in cache memory, high-speed graphics, and
data-acquisition applications. The CY7C150 has a memory reset feature that allows the entire memory to be reset in two
memory cycles.
A die coat is used to insure alpha immunity.
Logic Block Diagram
Pin Configuration
RS
D0 D1 D2 D3
64 x 64
ARRA
Y
Top View
A3
A4
A5
A6
A7
A8
A9
D0
D1
O0
O1
GND
WE
SENSE AMPS
ROW DECODER
DATAINPUT
CONTROL
A0
A1
A2
A3
A4
A5
DIP/SOIC
CS
OE
O0
O1
O2
O3
1
2
3
4
5
24
23
22
21
20
6 7C150 19
18
7
8
17
9
16
10
15
14
11
13
12
VCC
A2
A1
A0
RS
CS
WE
OE
D3
D2
O3
O2
COLUMN
COLUMN
DECODER
DECODER
A6
C150-2
C150–1
A7 A8 A9
Selection Guide
7C150−10
Maximum Access Time (ns)
7C150−12
7C150−15
7C150−25
10
12
15
25
12
15
25
35
90
90
90
90
100
Commercial
100
100
100
Military
Maximum Operating Current (mA)
Commercial
90
Military
Cypress Semiconductor Corporation
Document #: 38-05024 Rev. *A
•
3901 North First Street
•
San Jose
•
7C150−35
CA 95134 • 408-943-2600
Revised January 18, 2003
