54
CY7C451
CY7C453
CY7C454
512x9, 2Kx9, and 4Kx9 Cascadable
Clocked FIFOs with Programmable
Features
and write interfaces. Both FIFOs are 9 bits wide. The
CY7C451 has a 512-word by 9-bit memory array, the
CY7C453 has a 2048-word by 9-bit memory array, and the
CY7C454 has a 4096-word by 9-bit memory array. Devices
can be cascaded to increase FIFO depth. Programmable features include Almost Full/Empty flags and generation/checking
of parity. These FIFOs provide solutions for a wide variety of data
buffering needs, including high-speed data acquisition, multiprocessor interfaces, and communications buffering.
• High-speed, low-power, first-in first-out (FIFO)
memories
• 512 x 9 (CY7C451)
• 2,048 x 9 (CY7C453)
• 4,096 x 9 (CY7C454)
• 0.65 micron CMOS for optimum speed/power
• High-speed 83-MHz operation (12 ns read/write cycle
time)
• Low power — ICC=70 mA
• Fully asynchronous and simultaneous read and write
operation
• Empty, Full, Half Full, and programmable Almost Empty
and Almost Full status flags
• TTL compatible
• Retransmit function
• Parity generation/checking
• Output Enable (OE) pins
• Independent read and write enable pins
• Center power and ground pins for reduced noise
• Supports free-running 50% duty cycle clock inputs
• Width Expansion Capability
• Depth Expansion Capability
• Available in PLCC packages
Both FIFOs have 9-bit input and output ports that are controlled by separate clock and enable signals. The input port is
controlled by a free-running clock (CKW) and a write enable
pin (ENW). When ENW is asserted, data is written into the FIFO on
the rising edge of the CKW signal. While ENW is held active, data is
continually written into the FIFO on each CKW cycle. The output port
is controlled in a similar manner by a free-running read clock (CKR)
and a read enable pin (ENR). The read (CKR) and write (CKW)
clocks may be tied together for single-clock operation or the two
clocks may be run independently for asynchronous read/write applications. Clock frequencies up to 83.3 MHz are achievable in the standalone configuration, and up to 83.3 MHz is achievable when FIFOs
are cascaded for depth expansion.
Depth expansion is possible using the cascade input (XI) and
cascade output (XO). The XO signal is connected to the XI of the next
device, and the XO of the last device should be connected to the XI
of the first device. In standalone mode, the input (XI) pin is simply tied
to VSS.
In the standalone and width expansion configurations, a LOW
on the retransmit (RT) input causes the FIFOs to retransmit
the data. Read enable (ENR) and the write enable (ENW) must
both be HIGH during the retransmit, and then ENR is used to
access the data.
Functional Description
The CY7C451, CY7C453, and CY7C454 are high-speed,
low-power, first-in first-out (FIFO) memories with clocked read
D0 – 8
Logic Block Diagram
Pin Configurations
INPUT
REGISTER
CKW
PLCC/LCC
Top View
ENW
D0 D1 D2 D3 D4 D5 D6
FLAG/PARITY
PROGRAM
REGISTER
PARITY
WRITE
CONTROL
FLAG
LOGIC
RAM
ARRAY
512x 9
2048x 9
4096x9
WRITE
POINTER
MR
FL/RT
XI
HF
E/F
PAFE/XO
READ
POINTER
4 3 2 1 32 31 30
29
28
27
26
25
24
23
22
21
20
XI
ENW
CKW
VCC
VSS
HF
E/F
PAFE/XO
Q0
5
6
7
7C451
8
7C453
9
7C454
10
11
12
13
14 15 16 17 1819
Q1 Q2 Q3 Q4 Q5 Q6 Q7
RESET
LOGIC
EXPANSION
LOGIC
TRI–STATE
OUTPUT REGISTER
D7
D8
FL/RT
MR
VSS
CKR
ENR
OE
Q8 /PG/PE
C451-2
READ
CONTROL
OE
RETRANSMIT
LOGIC
Q0–7,Q8/PG/PE
Cypress Semiconductor Corporation
Document #: 38-06033 Rev. *A
•
CKR
ENR C451-1
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised December 27, 2002
