CY7C9915
PRELIMINARY
3.3V Programmable Skew Clock Buffer
Features
Functional Description
• All output pair skew <100 ps (typical)
The CY7C9915 RoboClock is a 150-MHz Low-voltage
Programmable Skew Clock Buffer that offers user-selectable
control over system clock functions. This multiple-output clock
driver provides the system integrator with functions necessary
to optimize the timing of high-performance computer systems.
Eight individual drivers, arranged as four pairs of user-controllable outputs, can each drive terminated transmission lines
with impedances as low as 50Ω while delivering minimal and
specified output skews and full-swing logic levels (LVTTL).
• Input Frequency Range: 3.75 MHz to 150 MHz
• Output Frequency Range: 3.75 MHz to 150 MHz
• User-selectable output functions
— Selectable skew to 18 ns
— Inverted and non-inverted
— Operation at 1⁄2 and 1⁄4 input frequency
— Operation at 2x and 4x input frequency (input as low
as 3.75 MHz)
• Zero input-to-output delay
• 3.3V power supply
• ± 3.0% Output Duty Cycle Distortion
• LVTTL outputs drive 50Ω terminated lines
• Low operating current
Each output can be hardwired to one of nine delay or function
configurations. Delay increments of 0.42 to 1.6 ns are determined by the operating frequency with outputs able to skew up
to ±6 time units from their nominal “zero” skew position. The
completely integrated PLL allows external load and transmission line delay effects to be canceled. When this “zero
delay” capability of the LVPSCB is combined with the
selectable output skew functions, the user can create
output-to-output delays of up to ±12 time units.
Divide-by-two and divide-by-four output functions are provided
for additional flexibility in designing complex clock systems.
When combined with the internal PLL, these divide functions
allow distribution of a low-frequency clock that can be multiplied by two or four at the clock destination. This facility
minimizes clock distribution difficulty while allowing maximum
system clock speed and flexibility.
• 32-pin PLCC package
• Jitter < 100ps peak-to-peak (< 15 ps RMS)
Block Diagram
Pin Configuration
2F1
TEST
GND
REF
1
32 31 30
29
4F0
28
27
GND
4F1
6
7
VCCQ
8
26
1F0
VCCN4
9
25
VCCN1
4Q1
10
24
1Q0
4Q0
11
23
1Q1
GND
12
22
GND
GND
13
21
GND
4Q0
4Q1
SKEW
3Q0
3Q1
CY7C9915
14 15 16 17 18 19 20
2F0
1F1
2Q0
2Q1
1Q0
1F0
1F1
Cypress Semiconductor Corporation
Document #: 38-07687 Rev. *A
VCCN2
2Q1
FB
2Q0
MATRIX
VCCN3
SELECT
INPUTS
(THREE
LEVEL)
SELECT
2F0
2F1
2
5
3Q1
3F0
3F1
3
3F1
FS
4F0
4F1
VCCQ
4
VCO AND
TIME UNIT
GENERATOR
3Q0
REF
FILTER
FS
PHASE
FREQ
DET
FB
3F0
TEST
1Q1
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised April 29, 2005
