ATM Multimode Fiber Transceivers
for SONET OC-3/SDH STM-1
in Low Cost 2 x 5 Package Style
Technical Data
HFBR-5905
1300 nm 2 km
Features
• Multisourced 2 x 5 Package
Style with MT-RJ Receptacle
• Single +3.3 V Power Supply
• Wave Solder and Aqueous
Wash Process Compatibility
• Manufactured in an ISO
9002 Certified Facility
• Full Compliance with ATM
Forum UNI SONET OC-3
Multimode Fiber Physical
Layer Specification
Applications
• Multimode Fiber ATM
Backbone Links
• Multimode Fiber ATM
Wiring Closet to Desktop
Links
Description
The HFBR-5900 family of transceivers from Hewlett-Packard
provide the system designer with
products to implement a range of
solutions for multimode fiber
SONET OC-3 (SDH STM-1)
physical layers for ATM and other
services.
These transceivers are all
supplied in the new industry
standard 2 x 5 DIP style with a
MT-RJ fiber connector interface.
ATM 2 km Backbone Links
The HFBR-5905 is a 1300 nm
product with optical performance
compliant with the SONET STS-3c
(OC-3) Physical Layer Interface
Specification. This physical layer
is defined in the ATM Forum UserNetwork Interface (UNI)
Specification Version 3.0. This
document references the ANSI
T1E1.2 specification for the details
of the interface for 2 km multimode
fiber backbone links.
The ATM 100 Mb/s-125 MBd
Physical Layer interface is best
implemented with the HFBR-5903
family of FDDI Transceivers
which are specified for use in this
4B/5B encoded physical layer per
the FDDI PMD standard.
Transmitter Sections
The transmitter section of the
HFBR-5905 utilizes a 1300 nm
InGaAsP LED. This LED is
packaged in the optical
subassembly portion of the
transmitter section. It is driven by
a custom silicon IC which
converts differential PECL logic
signals, ECL referenced (shifted)
to a +3.3 V supply, into an analog
LED drive current.
Receiver Sections
The receiver section of the
HFBR-5905 utilizes an InGaAs PIN
photodiode coupled to a custom
silicon transimpedance preamplifier IC. It is packaged in the
optical subassembly portion of the
receiver.
This PIN/preamplifier combination
is coupled to a custom quantizer
IC which provides the final pulse
shaping for the logic output and
the Signal Detect function. The
Data output is differential. The
Signal Detect output is singleended. Both Data and Signal
Detect outputs are PECL compatible, ECL referenced (shifted) to a
3.3 V power supply. The receiver
outputs, Data Out and Data Out
Bar, are squelched at Signal
Detect Deassert. That is, when the
light input power decreases to a
typical -38 dBm or less, the Signal
Detect Deasserts, i.e. the Signal
Detect output goes to a PECL low
state. This forces the receiver
outputs, Data Out and Data Out
Bar to go to steady PECL levels
High and Low respectively.
