HY57V161610D
2 Banks x 512K x 16 Bit Synchronous DRAM
DESCRIPTION
THE Hyundai HY57V161610D is a 16,777,216-bits CMOS Synchronous DRAM, ideally suited for the main memory and graphic
applications which require large memory density and high bandwidth. HY57V161610D is organized as 2banks of 524,288x16.
HY57V161610D is offering fully synchronous operation referenced to a positive edge clock. All inputs and outputs are synchronized
with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output
voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 1,2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A
burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a
new burst read or write command on any cycle. (This pipeline design is not restricted by a `2N` rule.)
FEATURES
•
Single 3.0V to 3.6V power supply
•
Auto refresh and self refresh
•
All device pins are compatible with LVTTL interface
•
4096 refresh cycles / 64ms
•
JEDEC standard 400mil 50pin TSOP-II with 0.8mm of pin
pitch
•
Programmable Burst Length and Burst Type
•
All inputs and outputs referenced to positive edge of system
clock
•
Data mask function by UDQM/LDQM
•
Internal two banks operation
- 1, 2, 4, 8 and Full Page for Sequence Burst
- 1, 2, 4 and 8 for Interleave Burst
•
Programmable CAS Latency ; 1, 2, 3 Clocks
ORDERING INFORMATION
Part No.
Clock Frequency
HY57V161610DTC-5
143MHz
HY57V161610DTC-8
400mil
50pin TSOP II
100MHz
HY57V161610DTC-15
LVTTL
125MHz
HY57V161610DTC-10
2Banks x 512Kbits x 16
166MHz
HY57V161610DTC-7
Package
183MHz
HY57V161610DTC-6
Interface
200MHz
HY57V161610DTC-55
Organization
66MHz
Note :
1. VDD(min) of HY57V161610DTC-5/55 is 3.15V
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for
use of circuits described. No patent licenses are implied
Rev. 4.0/Aug. 02
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