HIGH-SPEED 3.3V 32K x 36
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
IDT70V3579S
Features:
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True Dual-Port memory cells which allow simultaneous
access of the same memory location
High-speed clock to data access
– Commercial: 4.2/5/6ns (max.)
– Industrial: 5ns (max)
Pipelined output mode
Counter enable and reset features
Dual chip enables allow for depth expansion without
additional logic
Full synchronous operation on both ports
– 7.5ns cycle time, 133MHz operation (9.6 Gbps bandwidth)
– Fast 4.2ns clock to data out
– 1.8ns setup to clock and 0.7ns hold on all control, data, and
address inputs @ 133MHz
– Data input, address, byte enable and control registers
– Self-timed write allows fast cycle time
Separate byte controls for multiplexed bus and bus
matching compatibility
LVTTL- compatible, single 3.3V (±150mV) power supply for
core
LVTTL compatible, selectable 3.3V (±150mV)/2.5V (±125mV)
power supply for I/Os and control signals on each port
Industrial temperature range (-40°C to +85°C) is
available for selected speeds
Available in a 208-pin Plastic Quad Flatpack (PQFP) and
208-pin fine pitch Ball Grid Array, and 256-pin Ball Grid
Array
Green parts available, see ordering information
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Functional Block Diagram
BE3L
BE 3R
BE2L
BE 2R
BE1L
BE 1R
BE0L
BE 0R
R/WL
R/WR
B
W
0
L
CE0L
B
W
1
L
B B
WW
2 3
L L
B
W
3
R
BB
WW
2 1
RR
B
W
0
R
CE0R
CE1R
CE1L
OE L
OER
Dout0-8_L
Dout9-17_L
Dout18-26_L
Dout27-35_L
Dout0-8_R
Dout9-17_R
Dout18-26_R
Dout27-35_R
32K x 36
MEMORY
ARRAY
I/O0L- I/O35L
Din_L
I/O0R - I/O35R
Din_R
CLKL
CLKR
A14L
A 0L
CNTRSTL
ADSL
CNTENL
Counter/
Address
Reg.
,
A14R
ADDR_L
ADDR_R
Counter/
Address
Reg.
A0R
CNTRSTR
ADSR
CNTENR
4830 tbl 01
JULY 2008
1
©2008 Integrated Device Technology, Inc.
DSC 4830/15
