IDT71215
BiCMOS Static RAM
240K (16K x 15-Bit)
Cache-Tag RAM
for the Pentium™ Processor
Features
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stored TAG bits and the current Tag input data. An active HIGH
MATCH output is generated when these two groups of data are the
same for a given address. This high-speed MATCH signal, with tADM
as fast as 8ns, provides the fastest possible enabling of secondary
cache accesses.
The three separate I/O status bits (VLD, DTY, and WT) can be
configured for either dedicated or generic functionality, depending on
the SFUNC input pin. With SFUNC LOW, the status bits are defined
and used internally by the device, allowing easier determination of the
validity and use of the given Tag data. SFUNC HIGH releases the
defined internal status bit usage and control, allowing the user to
configure the status bit information to fit his system needs. A synchronous RESET pin, when held LOW at a rising clock edge, will reset all
status bits in the array for easy invalidation of all Tag addresses.
The IDT71215 also provides the option for Burst Ready (BRDY)
generation within the cache tag itself, based upon MATCH, VLD bit,
WT bit, and external inputs provided by the user. This can significantly
simplify cache controller logic and minimize cache decision time.
Match and Read operations are both asynchronous in order to
provide the fastest access times possible, while Write operations are
synchronous for ease of system timing.
The IDT71215 uses a 5V power supply on VCC with separate VCCQ
pins provided for the outputs to offer compliance with both 5V TTL and
3.3V LVTTL Logic levels. The PWRDN pin offers a low-power standby
mode to reduce power consumption by 90%, providing significant
system power savings.
The IDT71215 is fabricated using IDT’s high-performance, highreliability BiCMOS technology and is offered in a space-saving 80-pin
Thin Plastic Quad Flat Pack (TQFP) package.
16K x 15 Configuration
– 12 TAG Bits
– 3 Separate I/O Status Bits (Valid, Dirty, Write Through)
Match output uses Valid bit to qualify MATCH output
High-Speed Address-to-Match comparison times
– 8/9/10/12ns over commercial temperature range
BRDY circuitry included inside the Cache-Tag for
highest speed operation
Asynchronous Read/Match operation with Synchronous
Write and Reset operation
Separate WE for the TAG bits and the Status bits
Separate OE for the TAG bits, the Status bits, and BRDY
Synchronous RESET pin for invalidation of all Tag
entries
Dual Chip selects for easy depth expansion with no
performance degredation
I/O pins both 5V TTL and 3.3V LVTTL compatible with
VCCQ pins
PWRDN pin to place device in low-power mode
Packaged in a 80-pin Thin Plastic Quad Flat Pack (TQFP).
Description
The IDT71215 is a 245,760-bit Cache Tag Static RAM, organized 16K x 15 and designed to support the Pentium and other Intel
processors at bus speeds up to 66MHz. There are twelve common
I/O TAG bits, with the remaining three bits used as status bits. A 12bit comparator is on-chip to allow fast comparison of the twelve
Pin Descriptions
A0 – A13
Address Inputs
Input
CLK
System Clock
Input
CS1, CS2
Chip Selects
Input
BRDYH
BRDY Force High
Input
WET
Write Enable – Tag Bits
Input
BRDYOE
BRDY Output Enable
Input
WES
Write Enable – Status Bits
Input
BRDYIN
Additional BRDY Input
Input
OET
Output Enable – Tag Bits
Input
BRDY
Burst Ready
Output
OES
Output Enable – Status Bits
Input
TAG 0 – TAG11
Tag Data Input/Outputs
I/O
RESET
Status Bit Reset
Input
VLDOUT /S1OUT
Valid Bit/S1 Bit Output
Output
PWRDN
Pow erdown Mode Control Pin
Input
DTYOUT /S2OUT
Dirty Bit/S2 Bit Output
Output
SFUNC
Status Bit Function Control Pin
Input
WTOUT /S3OUT
Write Through Bit/S3 Bit Output
Output
W/R
Write/Read Input from Processor Input
MATCH
Match
Output
VLDIN/S1IN
Valid Bit/S1 Bit Input
Input
VCC
+5V Power
Pwr
DTYIN/S2IN
Dirty Bit/S2 Bit Input
Input
VCCQ
Output Buffer Power
QPwr
WTIN/S3IN
Write Through Bit/S3 Bit Input
Input
VSS
Ground
Gnd
3075 tbl 01
OCTOBER 1999
Pentium is a trademark of Intel Corporation.
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©1999 Integrated Device Technology, Inc.
DSC-3075/04
