CMOS SyncBiFIFOTM
256 x 36 x 2, 512 x 36 x 2,
1,024 x 36 x 2
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FEATURES:
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Memory storage capacity:
IDT723622 – 256 x 36 x 2
IDT723632 – 512 x 36 x 2
IDT723642 – 1,024 x 36 x 2
Free-running CLKA and CLKB may be asynchronous or
coincident (simultaneous reading and writing of data on a single
clock edge is permitted)
Two independent clocked FIFOs buffering data in opposite
directions
Mailbox bypass register for each FIFO
Programmable Almost-Full and Almost-Empty flags
Microprocessor Interface Control Logic
IRA, ORA, AEA, and AFA flags synchronized by CLKA
IRB, ORB, AEB, and AFB flags synchronized by CLKB
Supports clock frequencies up to 83MHz
Fast access times of 8ns
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IDT723622
IDT723632
IDT723642
Available in 132-pin Plastic Quad Flatpack (PQFP) or spacesaving 120-pin Thin Quad Flatpack (TQFP)
Low-power 0.8-Micron Advanced CMOS technology
Industrial temperature range (–40°C to +85°C) is available
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DESCRIPTION:
The IDT723622/723632/723642 are a monolithic, high-speed, low-power,
CMOS Bidirectional SyncFIFO (clocked) memory which supports clock frequencies up to 83MHz and have read access times as fast as 8ns. Two
independent 256/512/1,024 x 36 dual-port SRAM FIFOs on board each chip
buffer data in opposite directions. Communication between each port may
bypass the FIFOs via two 36-bit mailbox registers. Each mailbox register has
a flag to signal when new mail has been stored.
These devices are a synchronous (clocked) FIFO, meaning each port
employs a synchronous interface. All data transfers through a port are gated
to the LOW-to-HIGH transition of a port clock by enable signals. The clocks for
each port are independent of one another and can be asynchronous or
FUNCTIONAL BLOCK DIAGRAM
MBF1
RST1
FIFO1,
Mail1
Reset
Logic
Input
Register
Port-A
Control
Logic
Write
Pointer
36
IRA
AFA
RAM
ARRAY
256 x 36
512 x 36
1,024 x 36
Output
Register
Mail 1
Register
CLKA
CSA
W/RA
ENA
MBA
36
Read
Pointer
ORB
AEB
Status Flag
Logic
FIFO 1
Programmable Flag
Offset Registers
FS0
FS1
A0 - A35
B0 - B35
10
Read
Pointer
Output
Register
36
Status Flag
Logic
IRB
AFB
36
Write
Pointer
RAM
ARRAY
256 x 36
512 x 36
1,024 x 36
FIFO2,
Mail2
Reset
Logic
Input
Register
FIFO 2
ORA
AEA
Mail 2
Register
MBF2
RST2
Port-B
Control
Logic
CLKB
CSB
W/RB
ENB
MBB
3022 drw 01
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. SyncBiFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
DECEMBER 2001
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2001 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-3022/4
