79RC5000
MULTI-ISSUE
64-BIT MICROPROCESSOR
x
Large, efficient on-chip caches
– 32KB Instruction Cache, 32KB Data Cache
– 2-set associative in each cach
– Virtually indexed and physically tagged to minimize cache
flushes
– Write-back and write-through selectable on a per page basis
– Critical word first cache miss processing
– Supports back-to-back loads and stores in any combination at
full pipeline rate
x
High-performance memory system
– Large primary caches integrated on-chip
– Secondary cache control interface on-chip
– High-frequency 64-bit bus interface runs up to 125MHz
– Aggregate bandwidth of on-chip caches, system interface of
5.6GB/s
– High-performance write protocols for graphics and data
communications
x Compatible with a variety of operating systems
– Windows™ CE
– Numerous MIPS-compatible real-time operating systems
x Uses input system clock, with processor pipeline clock
multiplied by a factor of 2-8
x Industrial and commercial temperature range
VHUXWDH)
VHUXWDH)
VHUXWDH)
VHUXWDH)
x
Dual issue super-scalar execution core
– 250 MHz frequency
– Dual issue floating-point ALU operations with other instruction
classes
– Traditional 5-stage pipeline, minimizes load and branch latencies
x Single-cycle repeat rate for most floating point ALU
operations
x High level of performance for a variety of applications
– High-performance 64-bit integer unit achieves 330 dhrystone
MIPS (dhrystone 2.1)
– Ultra high-performance floating-point accelerator, directly
implementing single- and double-precision operations
achieves 500mflops
– Extremely large on-chip primary cache
– On-chip secondary cache controller
x MIPS-IV 64-bit ISA for improved computation
– Compound floating-point operations for 3D graphics and
floating-point DSP
– Conditional move operations
x Large on-chip TLB
x
Active power management, including use of WAIT operation
PDUJDL' NFRO%
PDUJDL' NFRO%
PDUJDL' NFRO%
PDUJDL' NFRO%
Phase Lock Loop
Data Set A
Instruction Set A
Data Tag A
Store B uffer
DT LB Physical
Instruction Select
SysAD
Integer Instruction Register
Address B uffer
W rite Buffer
FP Instruction Register
Instruction Tag A
Read Buffer
ITL B Physical
Data Set B
Instruction Set B
Instruction Tag B
DB us
FPIB us
IntIB us
Control
Tag
AuxTag
L oad Aligner
Unpacker/Packer
Joint T LB
Integer Register File
Coprocessor 0
System /M emory
Control
DVA
IVA
PC Increm enter
B ranch Adder
Instruction TL B Virtual
Integer Control
Floating Point
M Add,Add,Sub, Cvt
Div, SqRt
Floating-point Control
Floating Point Register File
Integer/Address Adder
Data T LB Virtual
Shifter/Store Aligner
Logic Unit
AB us
Integer M ultiply, Divide
Program Counter
The IDT logo is a registered trademark and RC32134, RC32364, RC64145, RC64474, RC64475, RC4650, RC4640, RC4600,RC4700 RC3081, RC3052, RC3051, RC3041, RISController, and RISCore are trademarks of Integrated Device Technology, Inc.
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2001 Integrated Device Technology, Inc.
April 10, 2001
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