®
ispLSI 2032V
3.3V High Density Programmable Logic
Features
Functional Block Diagram
• HIGH DENSITY PROGRAMMABLE LOGIC
1000 PLD Gates
32 I/O Pins, Two Dedicated Inputs
32 Registers
High Speed Global Interconnect
Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
• 3.3V LOW VOLTAGE 2032 ARCHITECTURE
N
• IN-SYSTEM PROGRAMMABLE
D Q
A5
Input Bus
D Q
A4
0139Bisp/2000
R
— 3.3V In-System Programmability Using Boundary
Scan Test Access Port (TAP)
— Open-Drain Output Option for Flexible Bus Interface
Capability, Allowing Easy Implementation of
Wired-OR or Bus Arbitration Logic
— Increased Manufacturing Yields, Reduced Time-toMarket and Improved Product Quality
Logic
Array
A6
D Q
A3
Electrically Erasable and Reprogrammable
Non-Volatile
100% Tested at Time of Manufacture
GLB
D
A2
D Q
A7
Output Routing Pool (ORP)
A1
EW
Input Bus
fmax = 100 MHz Maximum Operating Frequency
tpd = 7.5 ns Propagation Delay
Output Routing Pool (ORP)
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
—
—
—
—
—
Global Routing Pool
(GRP)
A0
— Interfaces With Standard 5V TTL Devices
— 60 mA Typical Active Current
— Fuse Map Compatible with 5V ispLSI 2032
ES
IG
N
S
—
—
—
—
—
FO
Description
VE
The ispLSI 2032V is a High Density Programmable Logic
Device that can be used in both 3.3V and 5V systems.
The device contains 32 Registers, 32 Universal I/O pins,
two Dedicated Input Pins, three Dedicated Clock Input
Pins, one dedicated Global OE input pin and a Global
Routing Pool (GRP). The GRP provides complete
interconnectivity between all of these elements. The
ispLSI 2032V features in-system programmability through
the Boundary Scan Test Access Port (TAP). The ispLSI
2032V offers non-volatile reprogrammability of the logic,
as well as the interconnect to provide truly reconfigurable
systems.
SI
20
Enhanced Pin Locking Capability
Three Dedicated Clock Input Pins
Synchronous and Asynchronous Clocks
Programmable Output Slew Rate Control
Flexible Pin Placement
Optimized Global Routing Pool Provides Global
Interconnectivity
The basic unit of logic on the ispLSI 2032V device is the
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. A7 (see Figure 1). There are a total of eight GLBs in the
ispLSI 2032V device. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.
pL
—
—
—
—
—
—
32
• THE EASE OF USE AND FAST SYSTEM SPEED OF
PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAs
U
SE
is
• ispDesignEXPERT™ – LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER™
— PC and UNIX Platforms
Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
2032v_10
1
September 2000
